Abstract: A system and method for generating simulated wiring connections between a semiconductor device and a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to the semiconductor device and identifying a plurality of second factors and instances of each second factor relating to the carrier. The first and second factors are associated with each other on a one-to-one basis. A simulated wiring connection is generated between a first I/O terminal and a matching second I/O terminal, subject to an identified instance of each first factor of each first I/O terminal being correlated to an identified instance of the associated second factor of the matching second I/O terminal. A simulated wiring connection is generated between third I/O terminals located in a first region and fourth I/O terminals located in said second region.

Abstract: A method of modifying a VLSI layout for performance optimization includes defining a revised set of ground rules for a plurality of original device shapes to be modified and flattening the plurality of original device shapes to a prime cell. A layout optimization operation is performed on the flattened device shapes, based on the revised set of ground rules, so as to create a plurality of revised device shapes. An overlay cell is then created from a difference between the revised device shapes and the original device shapes.

Abstract: A system and method for generating simulated wiring connections between first I/O terminals of a semiconductor device and second I/O terminals of a carrier. The method comprises identifying a plurality of first factors and instances of each first factor relating to a semiconductor device and identifying a plurality of second factors and instances of each second factor relating to a carrier. The first and second factors are associated with each other on a one-to-one basis. The instances of each first factor are correlated to the instances of each associated second factor on a one-to-one basis. A simulated wiring connection automatically is generated between each first I/O terminal and a matching second I/O terminal, subject to an identified instance of each first factor of each first I/O terminal being correlated to an identified instance of the associated second factor of the matching second I/O terminal.

Abstract: Disclosed is an Al-Ti-B master alloy especially designed to grain refine cast aluminum alloys containing silicon. The alloy composition goes contrary to present known art. Present commercial master alloys contain a ratio of Ti to B exceeding 2.2 to promote a mixture of TiB.sub.2 and TiAl.sub.3 crystals. This invention provides an Al-Ti-B alloy wherein the Ti to B ratio is 1. It contains a preponderance of mixed boride crystals. The optimum composition of the alloy of this invention is Al-3Ti-3B.