Abstract: A data processing apparatus and a method of processing data are disclosed, in which address translations between first addresses used in a first addressing system and second addresses used in a second addressing system are locally stored. Each stored address translation is stored with a corresponding identifier. In response to an invalidation command to perform an invalidation process on a selected stored address translation the selected stored address translation is invalidated, wherein the selected stored address translation is identified in the invalidation command by a specified first address and a specified identifier. The invalidation process is further configured by identifier grouping information which associates more than one identifier together as a group of identifiers, and the invalidation process is applied to all stored address translations which match the specified first address and which match any identifier in the group of identifiers to which the specified identifier belongs.

Abstract: A method and system for location of memory management translations in an emulated processor. The method includes: detecting a page miss of a process on an emulated processor, wherein the emulated processor software refills a translation lookaside buffer (TLB); locating a secondary data structure in memory; fetching a missing translation from a secondary data structure in memory; and inserting the missing translation in a guest translation lookaside buffer; wherein the steps are carried out in a trap handler in the emulated environment. The steps may be carried out in the emulated processor or in a host server of the emulated processor instead of invoking a guest operating system trap handler.

Abstract: A mechanism is provided for managing the translation look-aside buffer (TLB) of an emulated computer, in which an extension to the TLB is provided so as to improve virtual address translation capacity for the emulated central processing unit (CPU).

Abstract: A data processing apparatus and a method of processing data are disclosed, in which address translations between first addresses used in a first addressing system and second addresses used in a second addressing system are locally stored. Each stored address translation is stored with a corresponding identifier. In response to an invalidation command to perform an invalidation process on a selected stored address translation the selected stored address translation is invalidated, wherein the selected stored address translation is identified in the invalidation command by a specified first address and a specified identifier. The invalidation process is further configured by identifier grouping information which associates more than one identifier together as a group of identifiers, and the invalidation process is applied to all stored address translations which match the specified first address and which match any identifier in the group of identifiers to which the specified identifier belongs.

Abstract: A mechanism is provided for managing the translation look-aside buffer (TLB) of an emulated computer, in which an extension to the TLB is provided so as to improve virtual address translation capacity for the emulated central processing unit (CPU).

Abstract: A method and system for location of memory management translations in an emulated processor. The method includes: detecting a page miss of a process on an emulated processor, wherein the emulated processor software refills a translation lookaside buffer (TLB); locating a secondary data structure in memory; fetching a missing translation from a secondary data structure in memory; and inserting the missing translation in a guest translation lookaside buffer; wherein the steps are carried out in a trap handler in the emulated environment. The steps may be carried out in the emulated processor or in a host server of the emulated processor instead of invoking a guest operating system trap handler.

Abstract: A translator apparatus is provided with both program code interpreting and translating functionality, where subject program code is interpreted rather than being translated in those situations where interpretation of the subject program code is determined to be more beneficial. The translator applies an interpreting algorithm to determine whether a basic block of subject program code should be interpreted or translated. A particular subject of instructions supported by the interpreter functionality is initially selected from an entire instruction set for the subject program code. A basic block will be interpreted 1) if all of the instructions within a basic block are determined to be within the subset of instructions supported by the interpreter functionality, and 2) if an execution count of the basic block is below a translation threshold.

Abstract: A translator apparatus is provided with both program code interpreting and translating functionality, where subject program code is interpreted rather than being translated in those situations where interpretation of the subject program code is determined to be more beneficial. The translator applies an interpreting algorithm to determine whether a basic block of subject program code should be interpreted or translated. A particular subject of instructions supported by the interpreter functionality is initially selected from an entire instruction set for the subject program code. A basic block will be interpreted 1) if all of the instructions within a basic block are determined to be within the subset of instructions supported by the interpreter functionality, and 2) if an execution count of the basic block is below a translation threshold.