Abstract: Determining port failover information is described. First information is determined by a first storage processor executing first code for performing port matching. The first information identifies a first set of port pairs. Each port pair includes a first port of the first or second storage processor and a second port of the first or second storage processor. Each port pair denotes the first port as protecting the second port. Upon failure or unavailability of the second port, the first port virtualizes the second port and requests directed to the second port are redirected to the first port. Similarly, second information is determined by the second storage processor executing second code for performing the port matching. Port failover processing is performed upon failure or unavailability of port(s) of the first storage processor and/or the second storage processor. Port failover processing uses the first information and/or the second information.

Abstract: Described are techniques for coordinating processing to redirect requests. First and second storage processors of a data storage system are provided. Requests are directed to a first set of physical target ports of the first storage processor. The second storage processor is unavailable and has a second set of virtual target ports. Each virtual port of the second set is virtualized by a physical port of the first set. First processing is performed to redirect requests from the second set of virtual ports to a third set of physical ports of the second storage processor. First processing includes booting the second storage processor, directing requests to the third set of physical ports of the second storage processor rather than second set of virtual ports, and queuing requests received at the third set of physical ports until completion of pending requests previously received at the second set of virtual ports.

Abstract: The present disclosure provides a method for treating dry eye syndrome that comprises systemically administering to a patient in need thereof an effective amount of an androgen, including transdermal or subcutaneous delivery of the androgen.

Abstract: Method and system for managing port failover in storage system comprising first storage processor and first port and second storage processor and second port. Storage system adapted to communicate with FC switch. Storage system providing first and second names characterizing first and second ports to switch for registration such that the first name associated with first port and second name associated with second port. Storage system detects the state of first and second processors. Failure state in first or second processor activates deregistration of port associated therewith. Storage system providing to switch for re-registration one of the names in response to detecting failure in processor associated with one of the ports. The one of the names provided to switch such that the one of the names characterizing the one of the ports is associated with the other of the ports.

Abstract: A method is used in selecting iteration schemes for deduplication. An iteration scheme is selected. Based on the selection, sets of data are iterated. Based on the iteration, a deduplicating technique is applied to the sets of data. Based on the results of applying the deduplicating technique, the iteration scheme is changed. Based on an evaluation of a set of criteria, the iteration scheme is changed.

Abstract: A method is used in iterating for deduplication. A collection of data is selected from a set of storage extents. The collection of data is comprised of respective subset of the contents of each storage extent of the set of storage extents. A deduplicating technique is applied to the collection of data.

Abstract: Described are techniques for processing requests. A request is received at a data storage system. The request is a command to perform first processing and the request is sent from a client over a virtualized path. The virtualized path includes a virtual target port of the data storage system. The virtual target port is a first physical target port that provides a virtualized counterpart port for a second physical target port whereby requests directed to the second physical target port are routed to the first physical target port rather than the second physical target port. First processing is performed and a response to the request is generated. The response includes first information consistent with sending the request over a non-virtualized path to the second physical target port. The response is sent to the client.

Abstract: Memory is serviced. In response to an input indicating a serious condition, a service is invoked that is unaffected by the serious condition. By the service, it is determined whether other instructions are available to be executed that are not being affected by the serious condition. By the other instructions, data is copied from a write cache to a nonvolatile memory before the data is lost from the write cache.

Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board.

Abstract: SAS topology is managed. Internally within a SAS device on a SAS network, a performance characteristic of a PHY of the SAS device is monitored. Internally within the SAS device, it is determined, based on the performance characteristic, that the PHY has a problem, and, based on the determination, the PHY is affected to help prevent the PHY from adversely affecting communications on the SAS network.

Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board.

Abstract: Memory parameters are controlled. A power source capacity estimate is determined. Based on the power source capacity estimate, an amount of cache to enable is determined and is enabled.

Abstract: A data storage system has a chassis and a pair of printed circuit boards disposed in the chassis. Each one of the pair of printed circuit boards has disposed thereon a processor, a translator controlled by the processor, a SAS expander having a bidirectional front end port and multiple bidirectional backend ports, and an expansion port, and a SAS controller coupled between the translator and the expander. The system also has an interposer printed circuit board disposed in the chassis, and multiple multiplexers disposed on the interposer printed circuit board. Each one of the multiplexers has a pair of bidirectional front end ports and a pair of bidirectional back end ports. A first one of the pair of bidirectional front end ports is connected to a corresponding backend port of the SAS expander disposed on a first one of the pair of storage processor printed circuit boards.

Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board.

Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board.

Abstract: Data storage equipment includes a first storage processor comprising a processing circuit and a collection of packaged integrated circuit devices which has a first set of ports and a second set of ports; a second storage processor; and an interconnect coupled between the first and second storage processors. The processing circuit of the first storage processor is adapted to execute as follows. The collection of packaged integrated circuit devices of the first storage processor is configured to provide (i) communications to a set of storage devices through the first set of ports of the collection of packaged integrated circuit devices and (ii) other communications to the second storage processor through the second set of ports of the collection of packaged integrated circuit devices. Communications is passed between the first storage processor and the set of storage devices through the first set of ports of the collection of packaged integrated circuit devices.

Abstract: An improved data storage system has a set of storage devices, a first storage processor and a second storage processor for storing data into and retrieving data from the set of storage devices. The first storage processor includes a processing circuit and a packaged IC device which has a first set of ports and a second set of ports. The processing circuit is adapted to configure the packaged IC device to provide (i) communications to the set of storage devices through the first set of ports and (ii) other communications to the second storage processor through the second set of ports. The processing circuit is further adapted to pass communications between the first storage processor and the set of storage devices through the first set of ports; and pass communications between the first storage processor and the second storage processor through the second set of ports.

Abstract: A technique for managing data within a data storage system involves performing data storage operations on behalf of a set of hosts (i.e., one or more hosts) using a volatile-memory storage cache and a set of magnetic disk drives while the data storage system is being powered by a primary power source (e.g., a main power feed). The technique further involves receiving a power failure signal (e.g., from a sensor) indicating that the data storage system is now being powered by a backup power source rather than by the primary power source (e.g., due to a loss of the main power feed, due to a failure of a power converter, etc.), and moving data from the volatile-memory storage cache of the data storage system to a flash-based memory vault of the data storage system in response to the power failure signal.

Abstract: A data storage system has a chassis and a pair of printed circuit boards disposed in the chassis. Each one of the pair of printed circuit boards has disposed thereon a processor, a translator controlled by the processor, a SAS expander having a bidirectional front end port and multiple bidirectional backend ports, and an expansion port, and a SAS controller coupled between the translator and the expander. The system also has an interposer printed circuit board disposed in the chassis, and multiple multiplexers disposed on the interposer printed circuit board. Each one of the multiplexers has a pair of bidirectional front end ports and a pair of bidirectional back end ports. A first one of the pair of bidirectional front end ports is connected to a corresponding backend port of the SAS expander disposed on a first one of the pair of storage processor printed circuit boards.

Abstract: Memory parameters are controlled. A power source capacity estimate is determined. Based on the power source capacity estimate, an amount of cache to enable is determined and is enabled.