Patents by Inventor Matthew Marinella
Matthew Marinella has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11930723Abstract: An ionic redox transistor comprises a solid channel, a solid reservoir layer, and a solid electrolyte layer disposed between the channel and the reservoir layer. The channel exhibits a substantially linear current-voltage relationship in a first range of voltages, and a nonlinear current-voltage relationship in a second range of voltages that is greater than the first range of voltages. One or both of the substantially linear current-voltage relationship or the nonlinear current-voltage relationship of the channel is varied by changing the concentration of ions such as oxygen vacancies in the channel. Ion or vacancy transport between the channel and the reservoir layer across the electrolyte layer occurs in response to applying a voltage between the channel and the reservoir layer. Subject to the first range of voltages, the channel can function as a synapse device. Subject to the second range of voltages, the channel can function as a neuron device.Type: GrantFiled: November 9, 2021Date of Patent: March 12, 2024Assignee: National Technology & Engineering Solutions of Sandia, LLCInventors: Albert Alec Talin, Elliot James Fuller, Christopher Bennett, Tianyao Xiao, Matthew Marinella, Suhas Kumar
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Patent number: 11494464Abstract: An array circuit includes a plurality of vector-matrix multiplication (VMM) elements arranged in rows and columns. The VMM elements are configured to collectively perform multiplication of an input vector by a programmed input matrix to generate a plurality of output values that are representative of a result matrix that is the result of multiplication of the input vector and the input matrix. The VMM elements store states of the input matrix. Input voltages to the array are representative of elements of the input vector. A VMM element draws charge from a column read line based upon charging of a capacitor in the VMM. An integrator circuit connected to the column read line outputs a voltage that is indicative of a total charge drawn from the column read line by elements connected to the read line, which voltage is further indicative of an element of a result matrix.Type: GrantFiled: September 24, 2020Date of Patent: November 8, 2022Assignee: National Technology & Engineering Solutions of Sandia, LLCInventors: Sapan Agarwal, Matthew Marinella
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Patent number: 10950790Abstract: A two-terminal memory device and methods for its use are provided. In the device, a bottom electrode is electrically continuous with a first operating terminal, and a control gate electrode is electrically continuous with a second operating terminal. A stack of insulator layers comprising a hopping conduction layer and a tunnel layer is contactingly interposed between the bottom electrode and the control gate electrode. The tunnel layer is thinner than the hopping conduction layer, and it has a wider bandgap than the hopping conduction layer. The hopping conduction layer consists of a material that supports electron hopping transport.Type: GrantFiled: February 24, 2020Date of Patent: March 16, 2021Assignee: National Technology & Engineering Solutions of Sandia, LLCInventors: Matthew Marinella, Sapan Agarwal
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Patent number: 10776684Abstract: A method and apparatus for processing data. The data is sent to a processor unit comprising a group of neural cores, a group of digital processing cores, and a routing network connecting the group of digital processing cores. The data is processed in the processor unit to generate a result.Type: GrantFiled: November 2, 2016Date of Patent: September 15, 2020Assignee: National Technology & Engineering Solutions of Sandia, LLCInventors: Sapan Agarwal, Alexander H. Hsia, Matthew Marinella
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Patent number: 10489483Abstract: A method for programming substantially simultaneously more than one of the three-terminal memory cells that represent the values of a matrix to be multiplied by a vector is disclosed. Programming may be achieved by controlling the gate-drain voltage for more than one cell simultaneously to change each such cell's physical state and hence its effective resistance. Illustratively, the gates of each row of the cells corresponding to the matrix are coupled together and each coupled row is coupled to a respective controllable voltage source while the drains of each column of the cells of the matrix are coupled together and each coupled column is coupled to a respective controllable voltage source. The controllable voltage sources are arranged so that at the intersection of a row and a column, a cell experiences one of three conditions: increase effective resistance, decrease effective resistance, or substantially no change.Type: GrantFiled: September 21, 2018Date of Patent: November 26, 2019Assignee: National Technology & Engineering Solutions of Sandia, LLCInventors: Matthew Marinella, Sapan Agarwal
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Patent number: 10074522Abstract: The present invention relates to systems and methods for preparing reactively sputtered films. The films are generally thin transition metal oxide (TMO) films having an optimum stoichiometry for any useful device (e.g., a sub-stoichiometric thin film for a memristor device). Described herein are systems, methods, and calibrations processes that employ rapid control of partial pressures to obtain the desired film.Type: GrantFiled: March 27, 2015Date of Patent: September 11, 2018Assignee: National Technology & Engineering Solutions of Sandia, LLCInventors: James E. Stevens, Patrick R. Mickel, Andrew Lohn, Matthew Marinella
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Patent number: 10043855Abstract: Various technologies for improving uniformity of operation of elements in an array circuit are described herein. In an exemplary embodiment, a plurality of resistive elements are incorporated into an array circuit such that voltages developed across any two elements is substantially the same when an equal voltage is applied to energize the elements. In a crossbar array circuit that comprises a plurality of elements arranged in rows and columns, the resistance of each of the resistive elements is based upon a row or column to which the resistive element is connected.Type: GrantFiled: December 14, 2017Date of Patent: August 7, 2018Assignee: National Technology & Engineering Solutions of Sandia, LLCInventors: Sapan Agarwal, Matthew Marinella
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Patent number: 9761675Abstract: The present disclosure relates to resistive field structures that provide improved electric field profiles when used with a semiconductor device. In particular, the resistive field structures provide a uniform electric field profile, thereby enhancing breakdown voltage and improving reliability. In example, the structure is a field cage that is configured to be resistive, in which the potential changes significantly over the distance of the cage. In another example, the structure is a resistive field plate. Using these resistive field structures, the characteristics of the electric field profile can be independently modulated from the physical parameters of the semiconductor device. Additional methods and architectures are described herein.Type: GrantFiled: January 6, 2016Date of Patent: September 12, 2017Assignee: National Technology & Engineering Solutions of Sandia, LLCInventors: Matthew Marinella, Sandeepan DasGupta, Robert Kaplar, Albert G. Baca
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Patent number: 9336870Abstract: The present invention is directed generally to resistive random-access memory (RRAM or ReRAM) devices and systems, as well as methods of employing a thermal resistive model to understand and determine switching of such devices. In particular example, the method includes generating a power-resistance measurement for the memristor device and applying an isothermal model to the power-resistance measurement in order to determine one or more parameters of the device (e.g., filament state).Type: GrantFiled: February 3, 2015Date of Patent: May 10, 2016Assignee: Sandia CorporationInventors: Patrick R. Mickel, Conrad D. James, Andrew Lohn, Matthew Marinella, Alexander H. Hsia
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Patent number: 8872246Abstract: Apparatus is disclosed in which at least one resistive switching element is interposed between at least a first and a second conducting electrode element. The resistive switching element comprises a metal oxynitride. A method for making such a resistive switching element is also disclosed.Type: GrantFiled: January 25, 2013Date of Patent: October 28, 2014Assignee: Sandia CorporationInventors: James E. Stevens, Matthew Marinella, Andrew John Lohn