Patents by Inventor Matthew N. Rocklein
Matthew N. Rocklein has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20200251334Abstract: Methods, apparatuses, and systems related to formation of an atomic layer of germanium (Ge) on a substrate material are described. An example method includes introducing, into a semiconductor processing chamber housing a substrate material having a high aspect ratio, a reducing agent, and introducing, into the semiconductor processing chamber, a germanium amidinate precursor. The example method further includes forming an atomic layer of germanium on the substrate material resulting from a reaction of the reducing agent and the germanium amidinate precursor.Type: ApplicationFiled: February 6, 2019Publication date: August 6, 2020Inventors: Francois H. Fabreguette, Paul A. Paduano, Gurtej S. Sandhu, John A. Smythe, III, Matthew N. Rocklein
-
Publication number: 20200212299Abstract: Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. The barrier dielectric region serves to reduce an oxygen diffusion rate associated with the dielectric regions.Type: ApplicationFiled: March 9, 2020Publication date: July 2, 2020Inventors: Matthew N. Rocklein, D.V. Nirmal Ramaswamy
-
Publication number: 20200203350Abstract: Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.Type: ApplicationFiled: March 1, 2020Publication date: June 25, 2020Applicant: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Matthew N. Rocklein, Brett W. Busch
-
Patent number: 10600788Abstract: Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.Type: GrantFiled: June 8, 2018Date of Patent: March 24, 2020Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Matthew N. Rocklein, Brett W. Busch
-
Patent number: 10586923Abstract: Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. The barrier dielectric region serves to reduce an oxygen diffusion rate associated with the dielectric regions.Type: GrantFiled: July 28, 2017Date of Patent: March 10, 2020Assignee: Micron Technology, Inc.Inventors: Matthew N. Rocklein, D. V. Nirmal Ramaswamy
-
Publication number: 20190386015Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.Type: ApplicationFiled: August 26, 2019Publication date: December 19, 2019Inventors: Qian Tao, Matthew N. Rocklein, Beth R. Cook, Durai Vishak Nirmal Ramaswamy
-
Patent number: 10438643Abstract: Methods of operating a ferroelectric memory cell. The method includes applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell having a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. Another of the positive bias voltage and the negative bias voltage is applied to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Related ferroelectric memory cells include a ferroelectric material exhibiting asymmetric switching properties.Type: GrantFiled: November 19, 2018Date of Patent: October 8, 2019Assignee: Micron Technology, Inc.Inventors: Steven C. Nicholes, Ashonita A. Chavan, Matthew N. Rocklein
-
Patent number: 10403630Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.Type: GrantFiled: August 9, 2018Date of Patent: September 3, 2019Assignee: Micron Technology, Inc.Inventors: Qian Tao, Matthew N. Rocklein, Beth R. Cook, D. V. Nirmal Ramaswamy
-
Publication number: 20190267383Abstract: A DRAM capacitor comprising a first capacitor electrode configured as a container and comprising a doped titanium nitride material, a capacitor dielectric on the first capacitor electrode, and a second capacitor electrode on the capacitor dielectric. Methods of forming the DRAM capacitor are also disclosed, as are semiconductor devices and systems comprising such DRAM capacitors.Type: ApplicationFiled: February 23, 2018Publication date: August 29, 2019Inventors: Matthew N. Rocklein, Paul A. Paduano, Sanket S. Kelkar, Christopher W. Petz, Zhe Song, Vassil Antonov, Qian Tao
-
Publication number: 20190103151Abstract: Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.Type: ApplicationFiled: November 19, 2018Publication date: April 4, 2019Applicant: Micron Technology, Inc.Inventors: Steven C. Nicholes, Ashonita A. Chavan, Matthew N. Rocklein
-
Patent number: 10192605Abstract: Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.Type: GrantFiled: December 26, 2017Date of Patent: January 29, 2019Assignee: Micron Technology, Inc.Inventors: Steven C. Nicholes, Ashonita A. Chavan, Matthew N. Rocklein
-
Publication number: 20190027478Abstract: Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.Type: ApplicationFiled: June 8, 2018Publication date: January 24, 2019Applicant: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Matthew N. Rocklein, Brett W. Busch
-
Publication number: 20190027477Abstract: Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.Type: ApplicationFiled: July 21, 2017Publication date: January 24, 2019Inventors: GURTEJ S. SANDHU, MATTHEW N. ROCKLEIN, BRETT W. BUSCH
-
Patent number: 10177152Abstract: Some embodiments include an integrated capacitor assembly having a conductive pillar supported by a base, with the conductive pillar being included within a first electrode of a capacitor. The conductive pillar has a first upper surface. A dielectric liner is along an outer surface of the conductive pillar and has a second upper surface. A conductive liner is along the dielectric liner and is included within a second electrode of the capacitor. The conductive liner has a third upper surface. One of the first and third upper surfaces is above the other of the first and third upper surfaces. The second upper surface is at least as high above the base as said one of the first and third upper surfaces. Some embodiments include memory arrays having capacitors with pillar-type first electrodes.Type: GrantFiled: July 21, 2017Date of Patent: January 8, 2019Assignee: Micron Technology, Inc.Inventors: Gurtej S. Sandhu, Matthew N. Rocklein, Brett W. Busch
-
Publication number: 20180350824Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.Type: ApplicationFiled: August 9, 2018Publication date: December 6, 2018Inventors: Qian Tao, Matthew N. Rocklein, Beth R. Cook, D.V. Nirmal Ramaswamy
-
Patent number: 10147474Abstract: Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.Type: GrantFiled: December 26, 2017Date of Patent: December 4, 2018Assignee: Micron Technology, Inc.Inventors: Steven C. Nicholes, Ashonita A. Chavan, Matthew N. Rocklein
-
Patent number: 10062703Abstract: A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.Type: GrantFiled: March 15, 2017Date of Patent: August 28, 2018Assignee: Micron Technology, Inc.Inventors: Qian Tao, Matthew N. Rocklein, Beth R. Cook, D. V. Nirmal Ramaswamy
-
Publication number: 20180137905Abstract: Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.Type: ApplicationFiled: December 26, 2017Publication date: May 17, 2018Inventors: Steven C. Nicholes, Ashonita A. Chavan, Matthew N. Rocklein
-
Patent number: 9899072Abstract: Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.Type: GrantFiled: June 23, 2017Date of Patent: February 20, 2018Assignee: Micron Technology, Inc.Inventors: Steven C. Nicholes, Ashonita A. Chavan, Matthew N. Rocklein
-
Publication number: 20170346007Abstract: Semiconductor memory devices, resistive memory devices, memory cell structures, and methods of forming a resistive memory cell are provided. One example method of a resistive memory cell can include a number of dielectric regions formed between two electrodes, and a barrier dielectric region formed between each of the dielectric regions. The barrier dielectric region serves to reduce an oxygen diffusion rate associated with the dielectric regions.Type: ApplicationFiled: July 28, 2017Publication date: November 30, 2017Inventors: Matthew N. Rocklein, D.V. Nirmal Ramaswamy