Patents by Inventor Matthew Pascal DeLaquil
Matthew Pascal DeLaquil has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8819381Abstract: A system and method for storing and retrieving a sparse matrix from memory of a computing device while minimizing the amount of data stored and costly jumps in memory. The computing device may be an FPGA having memory and processing elements. The method comprises storing non-zero data elements of the matrix in a data array and storing their corresponding column address values in a column index array. To read this stored data from memory, each preceding value of the column index array may be compared with each current value of the column index array to determine if the data array value corresponding with the current column index array value belongs on the next row of the matrix. The method may include pre-ordering the matrix with zero-pad placeholders or creating a row increment pointer array which typically stores fewer values than the number of rows in the matrix.Type: GrantFiled: August 12, 2013Date of Patent: August 26, 2014Assignee: L-3 Communications Integrated Systems, L.P.Inventors: Scott Michael Burkart, Matthew Pascal DeLaquil, Deepak Prasanna, Joshua David Anderson
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Publication number: 20140032876Abstract: A system and method for storing and retrieving a sparse matrix from memory of a computing device while minimizing the amount of data stored and costly jumps in memory. The computing device may be an FPGA having memory and processing elements. The method comprises storing non-zero data elements of the matrix in a data array and storing their corresponding column address values in a column index array. To read this stored data from memory, each preceding value of the column index array may be compared with each current value of the column index array to determine if the data array value corresponding with the current column index array value belongs on the next row of the matrix. The method may include pre-ordering the matrix with zero-pad placeholders or creating a row increment pointer array which typically stores fewer values than the number of rows in the matrix.Type: ApplicationFiled: August 12, 2013Publication date: January 30, 2014Applicant: L-3 Communications Integrated Systems, L.P.Inventors: Scott Michael Burkart, Matthew Pascal DeLaquil, Deepak Prasanna, Joshua David Anderson
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Patent number: 8612723Abstract: A system and method for storing and retrieving a sparse matrix from memory of a computing device while minimizing the amount of data stored and costly jumps in memory. The computing device may be an FPGA having memory and processing elements. The method comprises storing non-zero data elements of the matrix in a data array and storing their corresponding column address values in a column index array. To read this stored data from memory, each preceding value of the column index array may be compared with each current value of the column index array to determine if the data array value corresponding with the current column index array value belongs on the next row of the matrix. The method may include pre-ordering the matrix with zero-pad placeholders or creating a row increment pointer array which typically stores fewer values than the number of rows in the matrix.Type: GrantFiled: May 6, 2008Date of Patent: December 17, 2013Assignee: L-3 Communications Integrated Systems, L.P.Inventors: Scott Michael Burkart, Matthew Pascal DeLaquil, Deepak Prasanna, Joshua David Anderson
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Patent number: 8375395Abstract: A computing architecture comprises a plurality of processing elements to perform data processing calculations, a plurality of memory elements to store the data processing results, and a reconfigurable interconnect network to couple the processing elements to the memory elements. The reconfigurable interconnect network includes a switching element, a control element, a plurality of processor interface units, a plurality of memory interface units, and a plurality of application control units. In various embodiments, the processing elements and the interconnect network may be implemented in a field-programmable gate array.Type: GrantFiled: January 3, 2008Date of Patent: February 12, 2013Assignee: L3 Communications Integrated Systems, L.P.Inventors: Deepak Prasanna, Matthew Pascal DeLaquil
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Patent number: 8166090Abstract: A system for solving linear equations comprises a first circuit including a first multiplication module for multiplying a first row of a matrix by a first instance of a vector variable to generate a first product, and a first linear solver module for calculating an updated first element of the vector variable using the first product. A second circuit includes a second multiplication module for multiplying a second row of the matrix by a second instance of the vector variable to generate a second product, and a second linear solver module for calculating an updated second element of the vector variable using the second product. An interface module updates the second instance of the vector variable with the first updated element, and updates the first instance of the vector variable with the second updated element.Type: GrantFiled: December 28, 2007Date of Patent: April 24, 2012Assignee: L3 Communications Integrated Systems, L.P.Inventors: Matthew Pascal DeLaquil, Deepak Prasanna, Scott Michael Burkart, Joshua D. Anderson, Antone Lee Kusmanoff
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Publication number: 20090282207Abstract: A system and method for storing and retrieving a sparse matrix from memory of a computing device while minimizing the amount of data stored and costly jumps in memory. The computing device may be an FPGA having memory and processing elements. The method comprises storing non-zero data elements of the matrix in a data array and storing their corresponding column address values in a column index array. To read this stored data from memory, each preceding value of the column index array may be compared with each current value of the column index array to determine if the data array value corresponding with the current column index array value belongs on the next row of the matrix. The method may include pre-ordering the matrix with zero-pad placeholders or creating a row increment pointer array which typically stores fewer values than the number of rows in the matrix.Type: ApplicationFiled: May 6, 2008Publication date: November 12, 2009Applicant: L-3 COMMUNICATIONS INTEGRATED SYSTEMS, L.P.Inventors: Scott Michael Burkart, Matthew Pascal DeLaquil, Deepak Prasanna, Joshua David Anderson
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Publication number: 20090178043Abstract: A computing architecture comprises a plurality of processing elements to perform data processing calculations, a plurality of memory elements to store the data processing results, and a reconfigurable interconnect network to couple the processing elements to the memory elements. The reconfigurable interconnect network includes a switching element, a control element, a plurality of processor interface units, a plurality of memory interface units, and a plurality of application control units. In various embodiments, the processing elements and the interconnect network may be implemented in a field-programmable gate array.Type: ApplicationFiled: January 3, 2008Publication date: July 9, 2009Applicant: L3 Communications Integrated Systems, L.P.Inventors: Deepak Prasanna, Matthew Pascal DeLaquil
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Publication number: 20090172052Abstract: A system for solving linear equations comprises a first circuit including a first multiplication module for multiplying a first row of a matrix by a first instance of a vector variable to generate a first product, and a first linear solver module for calculating an updated first element of the vector variable using the first product. A second circuit includes a second multiplication module for multiplying a second row of the matrix by a second instance of the vector variable to generate a second product, and a second linear solver module for calculating an updated second element of the vector variable using the second product. An interface module updates the second instance of the vector variable with the first updated element, and updates the first instance of the vector variable with the second updated element.Type: ApplicationFiled: December 28, 2007Publication date: July 2, 2009Applicant: L3 COMMUNICATIONS INTEGRATED SYSTEMS L.P.Inventors: Matthew Pascal DeLaquil, Deepak Prasanna, Scott Michael Burkart, Joshua D. Anderson