Patents by Inventor Matthew Peter Hutson

Matthew Peter Hutson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Asynchronous multi-clock system
    Patent number: 7929655
    Abstract: A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of the signals received from the clock domains have a common state; and gating circuitry for receiving the update signal and operable, when the update signal is set, to allow a next signal in the sequence to be received at the input of the first circuitry.
    Type: Grant
    Filed: June 9, 2009
    Date of Patent: April 19, 2011
    Assignee: STMicroelectronics Limited
    Inventor: Matthew Peter Hutson
  • ASYNCHRONOUS MULTI-CLOCK SYSTEM
    Publication number: 20090316845
    Abstract: A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of the signals received from the clock domains have a common state; and gating circuitry for receiving the update signal and operable, when the update signal is set, to allow a next signal in the sequence to be received at the input of the first circuitry.
    Type: Application
    Filed: June 9, 2009
    Publication date: December 24, 2009
    Applicant: STMICROELECTRONICS LIMITED
    Inventor: Matthew Peter Hutson
  • Asynchronous multi-clock system
    Patent number: 7545896
    Abstract: A system for controlling the transfer of a signal sequence in a first clock domain to a plurality of other clock domains. The system comprising: detecting circuitry for detecting receipt of the signals from the clock domains and setting an update signal when all of the signals received from the clock domains have a common state; and gating circuitry for receiving the update signal and operable, when the update signal is set, to allow a next signal in the sequence to be received at the input of the first circuitry.
    Type: Grant
    Filed: May 24, 2005
    Date of Patent: June 9, 2009
    Assignee: STMicroelectronics Limited
    Inventor: Matthew Peter Hutson