Patents by Inventor Matthew Prince

Matthew Prince has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240139432
    Abstract: Vascular access systems and methods are provided for ultrasound monitoring and integrated sensor array. A vascular access system can include a vascular access device, an ultrasound assembly, a securement dressing, a base unit, and one or more monitoring devices. The ultrasound assembly can include an ultrasound probe that can be positioned overtop a catheter that is inserted into a patient's vasculature and can be configured to allow one or more sensors to be integrated. Images from the ultrasound probe and readings from the one or more sensors can be processed to generate parameters representing status, events, or other information about the catheter. Display content including the images and the parameters can be provided to the monitoring devices.
    Type: Application
    Filed: September 25, 2023
    Publication date: May 2, 2024
    Inventors: Jonathan Karl Burkholz, Matthew Prince
  • Publication number: 20240139433
    Abstract: Vascular access systems and methods are provided for ultrasound monitoring. A vascular access system can include a vascular access device, an ultrasound assembly, a securement dressing, a base unit, and one or more monitoring devices. The ultrasound assembly can include an ultrasound probe that can be positioned overtop a catheter that is inserted into a patient's vasculature. Images from the ultrasound probe can be processed to generate parameters representing status, events, or other information about the catheter. Display content including the images and the parameters can be provided to the monitoring devices.
    Type: Application
    Filed: September 25, 2023
    Publication date: May 2, 2024
    Inventors: Jonathan Karl Burkholz, Matthew Prince
  • Publication number: 20070077765
    Abstract: A method including forming a hard mask and an etch stop layer over a sacrificial material patterned as a gate electrode, wherein a material for the hard mask and a material for the etch stop layer are selected to have a similar stress property; removing the material for the hard mask and the material for the etch stop layer sufficient to expose the sacrificial material; replacing the sacrificial material with another material. A system including a computing device including a microprocessor, the microprocessor including a plurality of transistor devices, at least one of the plurality of transistor devices including a gate electrode formed on a substrate surface; a discontinuous etch stop layer conformally formed on the substrate surface and adjacent side wall surfaces of the gate electrode; and a dielectric material conformally formed over the etch stop layer.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Inventors: Matthew Prince, Chris Barns, Justin Brask
  • Publication number: 20060135046
    Abstract: A multi-platen, multi-slurry chemical mechanical polishing method comprises providing a substrate having a surface that includes at least one nitride structure and an oxide layer atop the nitride structure, performing a first CMP process on the substrate using a first platen with a silica based slurry to remove a bulk portion of the oxide layer without exposing the nitride structure, performing a second CMP process on the substrate using a second platen with a ceria based slurry to remove a residual portion of the oxide layer and to expose at least a portion of the nitride structure, and performing a third CMP process on the substrate using the first platen with a silica based slurry to remove at least one defect caused by the ceria based slurry.
    Type: Application
    Filed: December 17, 2004
    Publication date: June 22, 2006
    Inventors: Matthew Prince, Mansour Moinpour, Francis Tambwe, Gary Ding
  • Publication number: 20060134916
    Abstract: A method of fabricating microelectronic structure using at least two material removal steps, such as for in a poly open polish process, is disclosed. In one embodiment, the first removal step may be chemical mechanical polishing (CMP) step utilizing a slurry with high selectivity to an interlevel dielectric layer used relative to an etch stop layer abutting a transistor gate. This allows the first CMP step to stop after contacting the etch stop layer, which results in substantially uniform “within die”, “within wafer”, and “wafer to wafer” topography. The removal step may expose a temporary component, such as a polysilicon gate within the transistor gate structure. Once the polysilicon gate is exposed other processes may be employed to produce a transistor gate having desired properties.
    Type: Application
    Filed: December 17, 2004
    Publication date: June 22, 2006
    Inventors: Matthew Prince, Francis Tambwe, Chris Barns
  • Publication number: 20050246344
    Abstract: A computer implemented method comprising receiving a list of one or more contact points from a sender and comparing the list of one or more contact points to a satellite server's do-not-contact list. Any contact point on the list of one or more contact points that appears on the satellite server's do-not-contact list is reported to the sender. The satellite server's do-not-contact list is generated from a do-not-contact list distributed by a master server. A registrant registers with the master server to provide a registrant contact point to be on the do-not-contact list to be distributed by the master server. The contact points in the registry may be organized in a hierarchy with preferences at one or more levels.
    Type: Application
    Filed: April 29, 2004
    Publication date: November 3, 2005
    Inventors: Arthur Keller, Lee Holloway, John Rodrigues, Dat Nguyen, Thomas Belote, Matthew Prince
  • Publication number: 20050170750
    Abstract: The present invention describes a method for creating a differential polish rate across a semiconductor wafer. The profile or topography of the semiconductor wafer is determined by locating the high points and low points of the wafer profile. The groove pattern of a polish pad is then adjusted to optimize the polish rate with respect to the particular wafer profile. By increasing the groove depth, width, and/or density of the groove pattern of the polish pad the polish rate may be increased in the areas that correspond to the high points of the wafer profile. By decreasing the groove depth, width, and/or density of the groove pattern of the polish pad the polish rate may be decreased in the areas that correspond to the low points of the wafer profile. A combination of these effects may be desirable in order to stabilize the polish rate across the wafer surface in order to improve the planarization of the polishing process.
    Type: Application
    Filed: March 24, 2005
    Publication date: August 4, 2005
    Inventors: Ebrahim Andideh, Matthew Prince
  • Publication number: 20050164609
    Abstract: Tantalum barrier layer chemical mechanical polishing may be improved by using suitably aged slurries. Slurries that are older than fifty days from their manufacture date result in significantly lower occurrences of defects.
    Type: Application
    Filed: January 22, 2004
    Publication date: July 28, 2005
    Inventors: Matthew Prince, Shaestagir Chowdhury, Brian Weselak, Jim Xu
  • Patent number: 6087733
    Abstract: A method and apparatus for compensating for the effects of nonuniform planarization in chemical-mechanical polishing (CMP) such as the erosion occurring from the removal of titanium nitride/tungsten films is disclosed. In the context of alignment marks, dummy marks are disposed on both sides of the actual alignment marks providing a similar feature density as the alignment marks. During the CMP, the dummy marks reside in the area of nonuniform erosion, leaving the actual marks in an area of uniform erosion. The present invention may also be used to control underlayer erosion variations in the high feature density device areas adjacent to the low feature density open areas by providing dummy features in the low feature density areas.
    Type: Grant
    Filed: June 12, 1998
    Date of Patent: July 11, 2000
    Assignee: Intel Corporation
    Inventors: Michael A. Maxim, Michael Kocsis, Ning Hsieh, Matthew Prince, Kenneth C. Cadien