Patents by Inventor Matthew R. Harrington
Matthew R. Harrington has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240087496Abstract: An electro-optic display having a plurality of pixels is driven from a first image to a second image using a first drive scheme, and then from the second image to a third image using a second drive scheme different from the first drive scheme and having at least one impulse differential gray level having an impulse potential different from the corresponding gray level in the first drive scheme. Each pixel which is in an impulse differential gray level in the second image is driven from the second image to the third image using a modified version of the second drive scheme which reduces its impulse differential The subsequent transition from the third image to a fourth image is also conducted using the modified second drive scheme but after a limited number of transitions using the modified second drive scheme, all subsequent transitions are conducted using the unmodified second drive scheme.Type: ApplicationFiled: November 15, 2023Publication date: March 14, 2024Inventors: Demetrious Mark HARRINGTON, Kenneth R. CROUNSE, Karl Raymond AMUNDSON, Teck Ping SIM, Matthew J. APREA
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Patent number: 9106138Abstract: A circuit is provided that includes a parasitic power circuit that powers a parasitic circuit. The parasitic power circuit derives a supply voltage from an external AC or other signal suitable for use as a communications signal. A PMOS transistor or transistors is utilized to enable a supply voltage capacitor to charge substantially to the same voltage as the channel voltage of the communications signal.Type: GrantFiled: April 1, 2014Date of Patent: August 11, 2015Assignee: Maxim Integrated Products, Inc.Inventors: Marvin L. Peak, Jr., Bradley M. Harrington, Matthew R. Harrington
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Patent number: 8698358Abstract: A circuit is provided that includes a parasitic power circuit that powers a parasitic circuit. The parasitic power circuit derives a supply voltage from an external AC or other signal suitable for use as a communications signal. A PMOS transistor or transistors is utilized to enable a supply voltage capacitor to charge substantially to the same voltage as the channel voltage of the communications signal.Type: GrantFiled: October 2, 2012Date of Patent: April 15, 2014Assignee: Maxim Integrated Products, Inc.Inventors: Marvin L. Peak, Jr., Bradley M. Harrington, Matthew R. Harrington
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Patent number: 7161866Abstract: A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.Type: GrantFiled: July 1, 2005Date of Patent: January 9, 2007Assignee: Micron Technology, Inc.Inventors: Matthew R. Harrington, Van C. Huynh, Adin E. Hyslop
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Patent number: 6914843Abstract: A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.Type: GrantFiled: June 12, 2002Date of Patent: July 5, 2005Assignee: Micron Technology, Inc.Inventors: Matthew R. Harrington, Van C. Huynh, Adin E. Hyslop
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Patent number: 6775192Abstract: A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.Type: GrantFiled: June 12, 2002Date of Patent: August 10, 2004Assignee: Micron Technology, Inc.Inventors: Matthew R. Harrington, Van C. Huynh, Adin E. Hyslop
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Patent number: 6674677Abstract: A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.Type: GrantFiled: June 12, 2002Date of Patent: January 6, 2004Assignee: Micron Technology, Inc.Inventors: Matthew R. Harrington, Van C. Huynh, Adin E. Hyslop
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Publication number: 20020190708Abstract: A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.Type: ApplicationFiled: June 12, 2002Publication date: December 19, 2002Applicant: Micron Technology, Inc.Inventors: Matthew R. Harrington, Van C. Huynh, Adin E. Hyslop
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Publication number: 20020149982Abstract: A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.Type: ApplicationFiled: June 12, 2002Publication date: October 17, 2002Applicant: Micron Technology, Inc.Inventors: Matthew R. Harrington, Van C. Huynh, Adin E. Hyslop
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Publication number: 20020149981Abstract: A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.Type: ApplicationFiled: June 12, 2002Publication date: October 17, 2002Applicant: Micron Technology, Inc.Inventors: Matthew R. Harrington, Van C. Huynh, Adin E. Hyslop
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Patent number: 6418070Abstract: A memory device tester capable of testing for proper operation of reduced power states in memory devices. The memory device tester can include a processor or a state machine, each configured to send commands to the memory device, and to compare results. An example of a memory device that can be tested by the memory device tester is a Direct Rambus Dynamic Random Access Memory (DRDRAM). The described processing systems and other circuits can test a DRDRAM for proper operation in a standby (STBY) state. When the DRDRAM is in STBY, the column decoder is shut off to conserve power, and the DRDRAM should not respond to column packets on the column control bus. The DRDRAM Specification suggests that the DRDRAM be put in the STBY state with no banks active. The method and apparatus provide for testing that the column decoder is shut off when in STBY with no banks active, which is the recommended usage pattern for the part.Type: GrantFiled: September 2, 1999Date of Patent: July 9, 2002Assignee: Micron Technology, Inc.Inventors: Matthew R. Harrington, Van C. Huynh, Adin E. Hyslop
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Patent number: 6134168Abstract: A counter (450) for generating a series of binary addresses, each of the addresses including a set of one or more most-significant bits. The counter includes circuitry to generate the addresses, including the set of most-significant bits (402), in a first mode and circuitry to generate the addresses (400), excluding the set of most significant bits, in a second mode. The counter is operable to transition between the first and second modes. The counter also includes circuitry to generate the addresses in the first mode in a non-binary count order in which the set of most-significant address bits is a set of least-significant bits in the count order.Type: GrantFiled: June 8, 1999Date of Patent: October 17, 2000Assignee: Texas Instruments IncorporatedInventors: Matthew R. Harrington, Steven C. Eplett, Kallol Mazumder, Scott E. Smith
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Patent number: 5999473Abstract: A counter (450) for generating a series of binary addresses, each of the addresses including a set of one or more most-significant bits. The counter includes circuitry to generate the addresses, including the set of most-significant bits (402), in a first mode and circuitry to generate the addresses (400), excluding the set of most significant bits, in a second mode. The counter is operable to transition between the first and second modes. The counter also includes circuitry to generate the addresses in the first mode in a non-binary count order in which the set of most-significant address bits is a set of least-significant bits in the count order.Type: GrantFiled: April 21, 1998Date of Patent: December 7, 1999Assignee: Texas Instruments IncorporatedInventors: Matthew R. Harrington, Steven C. Eplett, Kallol Mazumder, Scott E. Smith
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Patent number: D390773Type: GrantFiled: August 12, 1996Date of Patent: February 17, 1998Inventor: Matthew R. Harrington, Jr.