Patents by Inventor Matthew Richard Craig

Matthew Richard Craig has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240111450
    Abstract: A computer-implemented method for effectively delivering notifications in data storage environments includes, receiving, by a storage controller from a host system, a request to register the host system with the storage controller to receive notifications. These notifications may be associated with a selected type of event detected by the storage controller. In certain embodiments, the selected type of event is a space-related condition associated with a particular storage resource controlled by the storage controller. The computer-implemented method registers the host system with the storage controller. In response to detecting an event of the selected type on the storage controller, the computer-implemented method transmits a notification from the storage controller to the host system to provide notice of the event. A corresponding system and computer program product are also disclosed.
    Type: Application
    Filed: October 1, 2022
    Publication date: April 4, 2024
    Applicant: International Business Machines Corporation
    Inventors: Beth Ann Peterson, Matthew Richard Craig, John G. Thompson, John R. Paveza, Nicolas Marc Clayton, Terry O'Connor, David Michael Shackelford
  • Patent number: 11907543
    Abstract: Provided are a computer program product, system, and method for managing swappable data structures in a plurality of memory devices based on access counts of the data structures. Data structures indicated as swappable are updated less frequently than most frequently updated data structures. Data structures not indicated as swappable are maintained in a first level memory device and not moved to a second level memory device. The first level memory device has lower latency than the second level memory device. Access counts are maintained for the data structures stored in the first level memory device that are indicated as swappable. Data structures are selected in the first level memory device having lowest access counts. The selected data structures are removed from the first level memory device and retained in the second level memory device.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: February 20, 2024
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Beth Ann Peterson, Lokesh Mohan Gupta, Matthew G. Borlick, Matthew Richard Craig
  • Patent number: 11620055
    Abstract: Provided are computer program product, system, and method for managing data structures in a plurality of memory devices that are indicated to demote after initialization of the data structures. Indication is made to data structures to demote after initialization from a first level memory device to a second level memory device. The first level memory device has lower latency than the second level memory device. In response to completing initialization of the data structures in the first level memory device, the data structures indicated to demote after initialization are copied from the first level memory device to the second level memory device and removing the data structures indicate to move after initialization from the first level memory device.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: April 4, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Beth Ann Peterson, Lokesh Mohan Gupta, Matthew Richard Craig, Matthew G. Borlick
  • Patent number: 11573709
    Abstract: Provided are a computer program product, system, and method for maintaining data structures in a virtual memory comprised of a plurality of heterogeneous memory devices. Access counts are maintained for a plurality of data structures stored in a first level memory device. A determination is made of data structures in the first level memory device having lowest access counts. The determined data structures are deleted from the first level memory device and retaining copies of the data structures in a second level memory device, wherein the first level memory device has lower latency than the second level memory device.
    Type: Grant
    Filed: January 7, 2020
    Date of Patent: February 7, 2023
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Beth Ann Peterson, Lokesh Mohan Gupta, Matthew Richard Craig, Matthew G. Borlick
  • Patent number: 11294812
    Abstract: Provided are a computer program product, system, and method for prefetching cache resources for a write request from a host to tracks in storage cached in a cache. Cache resources held for a plurality of tracks in a write set are released before expected writes are received for the tracks in the write set. Cache resources for tracks in the write set are obtained, following the release of the cache resources, to use for expected write requests to the tracks in the write set.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: April 5, 2022
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Beth Ann Peterson, Chung Man Fung, Matthew J. Kalos, Matthew Richard Craig
  • Publication number: 20220043750
    Abstract: Provided are a computer program product, system, and method for prefetching cache resources for a write request from a host to tracks in storage cached in a cache. Cache resources held for a plurality of tracks in a write set are released before expected writes are received for the tracks in the write set. Cache resources for tracks in the write set are obtained, following the release of the cache resources, to use for expected write requests to the tracks in the write set.
    Type: Application
    Filed: August 4, 2020
    Publication date: February 10, 2022
    Inventors: Beth Ann PETERSON, Chung Man FUNG, Matthew J. KALOS, Matthew Richard CRAIG
  • Patent number: 11204802
    Abstract: Provided are techniques for adjusting a dispatch ratio for dispatching tasks from multiple queues. The dispatch ratio is set for each queue of a plurality of queues. A number of Central Processing Unit (CPU) cycles used by tasks from each of the plurality of queues during the interval is tracked. A CPU high percentage is determined that indicates a percentage of CPU cycles used by high priority tasks. In response to determining that the CPU high percentage is below a high threshold, a new dispatch ratio is calculated that indicates an increased number of high priority tasks are to be dispatched, and the new dispatch ratio is based on the CPU high percentage, the high threshold, and a current dispatches high value. The increased number of high priority tasks are dispatched from the high priority queue based on the new dispatch ratio during a new interval.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: December 21, 2021
    Assignee: International Business Machines Corporation
    Inventors: Matthew Richard Craig, Matthew J. Kalos, Matthew G. Borlick, Micah Robison, Lokesh Mohan Gupta
  • Publication number: 20210334133
    Abstract: Provided are techniques for adjusting a dispatch ratio for dispatching tasks from multiple queues. The dispatch ratio is set for each queue of a plurality of queues. A number of Central Processing Unit (CPU) cycles used by tasks from each of the plurality of queues during the interval is tracked. A CPU high percentage is determined that indicates a percentage of CPU cycles used by high priority tasks. In response to determining that the CPU high percentage is below a high threshold, a new dispatch ratio is calculated that indicates an increased number of high priority tasks are to be dispatched, and the new dispatch ratio is based on the CPU high percentage, the high threshold, and a current dispatches high value. The increased number of high priority tasks are dispatched from the high priority queue based on the new dispatch ratio during a new interval.
    Type: Application
    Filed: April 27, 2020
    Publication date: October 28, 2021
    Inventors: Matthew Richard Craig, Matthew J. Kalos, Matthew G. Borlick, Micah Robison, Lokesh Mohan Gupta
  • Publication number: 20210208792
    Abstract: Provided are a computer program product, system, and method for maintaining data structures in a virtual memory comprised of a plurality of heterogeneous memory devices. Access counts are maintained for a plurality of data structures stored in a first level memory device. A determination is made of data structures in the first level memory device having lowest access counts. The determined data structures are deleted from the first level memory device and retaining copies of the data structures in a second level memory device, wherein the first level memory device has lower latency than the second level memory device.
    Type: Application
    Filed: January 7, 2020
    Publication date: July 8, 2021
    Inventors: Beth Ann PETERSON, Lokesh Mohan GUPTA, Matthew Richard CRAIG, Matthew G. BORLICK
  • Publication number: 20210208791
    Abstract: Provided are a computer program product, system, and method for managing swappable data structures in a plurality of memory devices based on access counts of the data structures. Data structures indicated as swappable are updated less frequently than most frequently updated data structures. Data structures not indicated as swappable are maintained in a first level memory device and not moved to a second level memory device. The first level memory device has lower latency than the second level memory device. Access counts are maintained for the data structures stored in the first level memory device that are indicated as swappable. Data structures are selected in the first level memory device having lowest access counts. The selected data structures are removed from the first level memory device and retained in the second level memory device.
    Type: Application
    Filed: January 7, 2020
    Publication date: July 8, 2021
    Inventors: Beth Ann Peterson, Lokesh Mohan Gupta, Matthew G. Borlick, Matthew Richard Craig
  • Publication number: 20210208790
    Abstract: Provided are computer program product, system, and method for managing data structures in a plurality of memory devices that are indicated to demote after initialization of the data structures. Indication is made to data structures to demote after initialization from a first level memory device to a second level memory device. The first level memory device has lower latency than the second level memory device. In response to completing initialization of the data structures in the first level memory device, the data structures indicated to demote after initialization are copied from the first level memory device to the second level memory device and removing the data structures indicate to move after initialization from the first level memory device.
    Type: Application
    Filed: January 7, 2020
    Publication date: July 8, 2021
    Inventors: Beth Ann Peterson, Lokesh Mohan Gupta, Matthew Richard Craig, Matthew G. Borlick