Patents by Inventor Matthew Sean Grady

Matthew Sean Grady has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240213217
    Abstract: An apparatus includes a chip package that has a chip connection surface and has an array of micro-bumps on the chip connection surface. The array of micro-bumps includes a plurality of subarrays of micro-bumps. Micro-bumps within each subarray are spaced apart by a chip pitch and the subarrays within the array are spaced apart by a card pitch that is an integer multiple of the chip pitch. The apparatus also includes a laminate circuit card that has a card connection surface that faces the chip connection surface of the chip package and that has an array of card pads adjacent to the card connection surface. The card pads are spaced apart by the card pitch, and each of the card pads is aligned to and electrically connected with a corresponding subarray of micro-bumps. In some embodiments, an interposer connects the card pads to the micro-bumps, and may include decoupling capacitors.
    Type: Application
    Filed: December 21, 2022
    Publication date: June 27, 2024
    Inventors: David Michael Audette, Grant Wagner, Steven Paul Ostrander, Hubert Harrer, Arvind Kumar, Thomas Anthony Wassick, Matthew Sean Grady, Sungjun Chun
  • Patent number: 7139944
    Abstract: A method and system for determining minimum post production test time on an integrated circuit device to achieve optimal reliability of that device utilizing defect counts. The number of defective cells or active elements with defective cells (DEFECTS) on the integrated circuit device are counted and this count serves as a basis for determining the minimum test time. A higher number of DEFECTS results in longer post production testing in order to achieve optimum reliability of the integrated circuit device. The number of DEFECTS can be counted on a device internal to the integrated circuit device and made available to determine the minimum required test time. The number of DEFECTS can also be obtained external to the integrated circuit device by intercepting information routed to another device. Information provided internally and externally can also reveal the physical location of DEFECTS to further refine the minimum required test time.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: November 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Tange Nan Barbour, Thomas S. Barnett, Matthew Sean Grady, William Vincent Huott, Michael Richard Ouellette
  • Patent number: 6754864
    Abstract: A built-in self-test (BIST) system and method for testing an array of embedded electronic devices, the BIST comprising: a shift register device connected to an output pin of an embedded array of electronic devices being tested and for receiving a failure indication signal at a real-time output pin of the device under test, the shift register generating a unique signature in response to receipt of the failure indication; a device for determining whether the generated unique signature is represented in a table comprising known signature values and corresponding bitmaps of prior determined array defects for that device under test; wherein the need to bitmap the array is avoided when a known failure signature is determined.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: June 22, 2004
    Assignee: International Business Machines Corporation
    Inventors: David V. Gangl, Matthew Sean Grady, David John Iverson, Gary William Maier, Robert Edward Shearer, Donald Lawrence Wheater
  • Patent number: 6557132
    Abstract: A method for determining common failure modes of an integrated circuit device under test is disclosed. In an exemplary embodiment of the invention, a test pattern is applied to a series of inputs of the device under test. A set of output data generated by the device under test is then compared to a set of expected data, with the set of output data being generated by the device under test in response to the test pattern. It is then determined whether the set of output data has passed the test, with the set of output data passing the test if the set of output data matches the set of expected data. If the set of output data has not passed the test, then it is determined whether an output signature corresponding to the set of output data matches a previously stored output signature. Fail data corresponding to the output signature is then stored if the output signature matches a previously stored output signature.
    Type: Grant
    Filed: February 22, 2001
    Date of Patent: April 29, 2003
    Assignee: International Business Machines Corporation
    Inventors: David V. Gangl, Matthew Sean Grady, David John Iverson, Kenneth A. Lavallee, Robert Edward Shearer
  • Publication number: 20020116675
    Abstract: A method for determining common failure modes of an integrated circuit device under test is disclosed. In an exemplary embodiment of the invention, a test pattern is applied to a series of inputs of the device under test. A set of output data generated by the device under test is then compared to a set of expected data, with the set of output data being generated by the device under test in response to the test pattern. It is then determined whether the set of output data has passed the test, with the set of output data passing the test if the set of output data matches the set of expected data. If the set of output data has not passed the test, then it is determined whether an output signature corresponding to the set of output data matches a previously stored output signature. Fail data corresponding to the output signature is then stored if the output signature matches a previously stored output signature.
    Type: Application
    Filed: February 22, 2001
    Publication date: August 22, 2002
    Applicant: International Business Machines Corporation
    Inventors: David V. Gangl, Matthew Sean Grady, David John Iverson, Kenneth A. Lavallee, Robert Edward Shearer
  • Publication number: 20020116676
    Abstract: A built-in self-test (BIST) system and method for testing an array of embedded electronic devices, the BIST comprising: a shift register device connected to an output pin of an embedded array of electronic devices being tested and for receiving a failure indication signal at a real-time output pin of the device under test, the shift register generating a unique signature in response to receipt of the failure indication; a device for determining whether the generated unique signature is represented in a table comprising known signature values and corresponding bitmaps of prior determined array defects for that device under test; wherein the need to bitmap the array is avoided when a known failure signature is determined.
    Type: Application
    Filed: February 22, 2001
    Publication date: August 22, 2002
    Applicant: International Business Machines Corporation
    Inventors: David V. Gangl, Matthew Sean Grady, David John Iverson, Gary William Maier, Robert Edward Shearer, Donald Lawrence Wheater