Abstract: A microelectronic device comprises a stack structure overlying a source tier. The stack structure comprising a vertically alternating sequence of conductive structures and insulative structures arranged in tiers. The microelectronic device comprises a staircase structure within the stack structure and having steps comprising lateral edges of the tiers, support structures vertically extending through the stack structure and within a horizontal area of the staircase structure, and conductive contacts vertically extending through the stack structure and horizontally neighboring the support structures within the horizontal area of the staircase structure. Each of the conductive contacts has a horizontally projecting portion in contact with one of the conductive structures of the stack structure at one of the steps of the staircase structure. Related memory devices, electronic systems, and methods of forming the microelectronic devices are also described.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating first and second levels. A panel extends through the stack. The first levels have proximal regions adjacent the panel, and have distal regions further from the panel than the proximal regions. The distal regions include conductive structures. The conductive structures have a first thickness. The proximal regions include insulative structures. The insulative structures have a second thickness at least about as large as the first thickness. Some embodiments include methods of forming integrated assemblies.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The second tiers comprise doped silicon dioxide and the first tiers comprise a material other than doped silicon dioxide. The stack comprises laterally-spaced memory-block regions. Channel-material-string constructions extend through the first tiers and the second tiers in the memory-block regions. The doped silicon dioxide that is in the second tiers is etched selectively relative to said other material that is in the first tiers and selectively relative to and to expose an undoped silicon dioxide-comprising string of a charge-blocking material that is part of individual of the channel-material-string constructions. Structure independent of method is disclosed.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and nonterminal regions. The terminal regions are vertically thicker than the nonterminal regions. Channel material extends vertically through the stack. Tunneling material is adjacent the channel material. Charge-storage material is adjacent the tunneling material. High-k dielectric material is between the charge-storage material and the terminal regions of the conductive levels. The insulative levels have carbon-containing first regions between the terminal regions of neighboring conductive levels, and have second regions between the nonterminal regions of the neighboring conductive levels. Some embodiments include methods of forming integrated assemblies.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and nonterminal regions. The terminal regions are vertically thicker than the nonterminal regions. Channel material extends vertically through the stack. Tunneling material is adjacent the channel material. Charge-storage material is adjacent the tunneling material. High-k dielectric material is between the charge-storage material and the terminal regions of the conductive levels. The insulative levels have carbon-containing first regions between the terminal regions of neighboring conductive levels, and have second regions between the nonterminal regions of the neighboring conductive levels. Some embodiments include methods of forming integrated assemblies.

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The second tiers comprise doped silicon dioxide and the first tiers comprise a material other than doped silicon dioxide. The stack comprises laterally-spaced memory-block regions. Channel-material-string constructions extend through the first tiers and the second tiers in the memory-block regions. The channel-material-string constructions individually comprise a channel-material string that extends through the first tiers and the second tiers in the memory-block regions. The doped silicon dioxide that is in the second tiers is etched selectively relative to said other material that is in the first tiers and selectively relative to and to expose an undoped silicon dioxide-comprising string of a charge-blocking material that is part of individual of the channel-material-string constructions.

Abstract: Some embodiments include an integrated assembly having a vertical stack of alternating insulative and conductive levels. The conductive levels have terminal regions and nonterminal regions. The terminal regions are vertically thicker than the nonterminal regions. Channel material extends vertically through the stack. Tunneling material is adjacent the channel material. Charge-storage material is adjacent the tunneling material. High-k dielectric material is between the charge-storage material and the terminal regions of the conductive levels. The insulative levels have carbon-containing first regions between the terminal regions of neighboring conductive levels, and have second regions between the nonterminal regions of the neighboring conductive levels. Some embodiments include methods of forming integrated assemblies.

Abstract: Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.

Abstract: Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.

Abstract: Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.

Abstract: Integrated circuitry comprising an array comprises a plurality of conductive vias. Individual of the vias comprise an upper horizontal perimeter comprising opposing end portions. One of the opposing end portions comprises opposing straight sidewalls. The other of the opposing end portions comprises opposing curved sidewalls that join with the opposing straight sidewalls of the one opposing end portion. Other embodiments, including methods, are disclosed.

Abstract: The embodiments herein relate to methods and apparatus for determining whether a particular test bath is able to successfully fill a feature on a substrate. In various cases, the substrate is a semiconductor substrate and the feature is a through-silicon-via. Generally, two experiments are used: a first experiment simulates the conditions present in a field region of the substrate during the fill process, and the second experiment simulates the conditions present in a feature on the substrate during the fill process. The output from these experiments may be used with various techniques to predict whether the particular bath will result in an adequately filled feature.

Abstract: Apparatus and methods for electroplating metal onto substrates are disclosed. The electroplating apparatus comprise an electroplating cell and at least one oxidization device. The electroplating cell comprises a cathode chamber and an anode chamber separated by a porous barrier that allows metal cations to pass through but prevents organic particles from crossing. The oxidation device (ODD) is configured to oxidize cations of the metal to be electroplated onto the substrate, which cations are present in the anolyte during electroplating. In some embodiments, the ODD is implemented as a carbon anode that removes Cu(I) from the anolyte electrochemically. In other embodiments, the ODD is implemented as an oxygenation device (OGD) or an impressed current cathodic protection anode (ICCP anode), both of which increase oxygen concentration in anolyte solutions. Methods for efficient electroplating are also disclosed.

Abstract: The embodiments herein relate to methods and apparatus for determining whether a particular test bath is able to successfully fill a feature on a substrate. In various cases, the substrate is a semiconductor substrate and the feature is a through-silicon-via. Generally, two experiments are used: a first experiment simulates the conditions present in a field region of the substrate during the fill process, and the second experiment simulates the conditions present in a feature on the substrate during the fill process. The output from these experiments may be used with various techniques to predict whether the particular bath will result in an adequately filled feature.

Abstract: The embodiments herein relate to methods and apparatus for determining whether a particular test bath is able to successfully fill a feature on a substrate. In various cases, the substrate is a semiconductor substrate and the feature is a through-silicon-via. Generally, two experiments are used: a first experiment simulates the conditions present in a field region of the substrate during the fill process, and the second experiment simulates the conditions present in a feature on the substrate during the fill process. The output from these experiments may be used with various techniques to predict whether the particular bath will result in an adequately filled feature.

Abstract: Prior to electrodeposition, a semiconductor wafer having one or more recessed features, such as through silicon vias (TSVs), is pretreated by contacting the wafer with a pre-wetting liquid comprising a buffer (such as a borate buffer) and having a pH of between about 7 and about 13. This pre-treatment is particularly useful for wafers having acid-sensitive nickel-containing seed layers, such as NiB and NiP. The pre-wetting liquid is preferably degassed prior to contact with the wafer substrate. The pretreatment is preferably performed under subatmospheric pressure to prevent bubble formation within the recessed features. After the wafer is pretreated, a metal, such as copper, is electrodeposited from an acidic electroplating solution to fill the recessed features on the wafer. The described pretreatment minimizes corrosion of seed layer during electroplating and reduces plating defects.

Abstract: Prior to electrodeposition, a semiconductor wafer having one or more recessed features, such as through silicon vias (TSVs), is pretreated by contacting the wafer with a pre-wetting liquid comprising a buffer (such as a borate buffer) and having a pH of between about 7 and about 13. This pre-treatment is particularly useful for wafers having acid-sensitive nickel-containing seed layers, such as NiB and NiP. The pre-wetting liquid is preferably degassed prior to contact with the wafer substrate. The pretreatment is preferably performed under subatmospheric pressure to prevent bubble formation within the recessed features. After the wafer is pretreated, a metal, such as copper, is electrodeposited from an acidic electroplating solution to fill the recessed features on the wafer. The described pretreatment minimizes corrosion of seed layer during electroplating and reduces plating defects.

Abstract: The embodiments herein relate to methods and apparatus for determining whether a particular test bath is able to successfully fill a feature on a substrate. In various cases, the substrate is a semiconductor substrate and the feature is a through-silicon-via. Generally, two experiments are used: a first experiment simulates the conditions present in a field region of the substrate during the fill process, and the second experiment simulates the conditions present in a feature on the substrate during the fill process. The output from these experiments may be used with various techniques to predict whether the particular bath will result in an adequately filled feature.

Abstract: Apparatus and methods for electroplating metal onto substrates are disclosed. The electroplating apparatus comprise an electroplating cell and at least one oxidization device. The electroplating cell comprises a cathode chamber and an anode chamber separated by a porous barrier that allows metal cations to pass through but prevents organic particles from crossing. The oxidation device (ODD) is configured to oxidize cations of the metal to be electroplated onto the substrate, which cations are present in the anolyte during electroplating. In some embodiments, the ODD is implemented as a carbon anode that removes Cu(I) from the anolyte electrochemically. In other embodiments, the ODD is implemented as an oxygenation device (OGD) or an impressed current cathodic protection anode (ICCP anode), both of which increase oxygen concentration in anolyte solutions. Methods for efficient electroplating are also disclosed.