Abstract: A method for receiving packet data at a communication channel and transmitting the packet data over serial links of the communication channel. The packet data is sliced into n-bit data portions which are concatenated with a header prior to transmitting an n-bit portion across one of the serial links of the communication channel. The header may include an invert bit to alter the majority sign of an n-bit portion. Other aspects of the present invention are also described herein.

Abstract: Disclosed are, inter alia, methods, apparatus, computer-storage media, mechanisms, and means associated with a shift register with a dynamic entry point, which may particularly useful for aligning skewed data. The dynamic entry shift register typically includes a series of storage elements, with multiplexers distributed between the storage elements. Each of the multiplexers is configured to select between: (a) the output signal of a previous storage element, and (b) the input signal. A control is configured to configure the multiplexers for a data signal applied as the input signal to induce an appropriate delay of the data signal as the output signal. The dynamic entry shift register can be scaled to accommodate a longer delay while still using only 2:1 multiplexers between stages in the dynamic entry shift register(s).

Abstract: A channel synchronization method in which local serializers serially transmits first n-bit codes, respectively, to remote deserializers, respectively. Also local deserializers serially receive first n-bit codes, respectively, from remote serializers, respectively. One of the first n-bit codes transmitted to one of the remote serializers indicates one of the local deserializers is not link aligned.

Abstract: Network switching and/or routing devices can use switching fabrics that gather information about output port buffer status and distribute that information to various line cards for use in data frame congestion avoidance. The switching fabric can gather output buffer status information for all output ports and distribute that information to each line card in an efficient, in-band manner. Individual line cards can use the information to determine from which line card virtual output queue to dequeue data frames destined for the switching fabric. Line cards can also gather output buffer status information associated with line card queues used for receiving data from the switching fabric. Such data is used in a manner similar to the output buffer data from the switching fabric.

Abstract: Network switching and/or routing devices can use switching fabrics that gather information about output port buffer status and distribute that information to various line cards for use in data frame congestion avoidance. The switching fabric can gather output buffer status information for all output ports and distribute that information to each line card in an efficient, in-band manner. Individual line cards can use the information to determine from which line card virtual output queue to dequeue data frames destined for the switching fabric. Line cards can also gather output buffer status information associated with line card queues used for receiving data from the switching fabric. Such data is used in a manner similar to the output buffer data from the switching fabric.

Abstract: A network accelerator for TCP/IP includes programmable logic for performing network protocol processing at network signaling rates. The programmable logic is configured in a parallel pipelined architecture controlled by state machines and implements processing for predictable patterns of the majority of transmissions. Incoming packets are compared with patterns corresponding to classes of transmissions which are stored in a content addressable memory, and are simultaneously stored in a dual port, dual bank application memory. The patterns are used to determine sessions to which an incoming IP datagram belongs, and data packets stored in the application memory are processed by the programmable logic. Processing of packet headers is performed in parallel and during memory transfers without the necessity of conventional store and forward techniques resulting in a substantial reduction in latency. Packets which constitute exceptions or which have checksum or other errors are processed in software.