Abstract: The disclosure describes a multi-stage phase comparator and a phase-locked loop incorporating such a comparator. The comparator measures a phase difference between a reference signal and an output signal using a periodic clock. The comparator is a two stage comparator comprising a fine and coarse comparator. The coarse comparator measures the number of full clock periods between a transition of the reference signal and the output signal. The fine comparator comprises a delay line generator that generates a plurality of delayed clocks. The delayed clocks are used to over sample the reference signal to determine a fine phase difference representing a remaining fraction of the clock period, between transitions of the reference and output signals. A phase locked loop using the multi-stage comparator allows for more accurate phase locking.