Patents by Inventor Matthew W. Brocker
Matthew W. Brocker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9436248Abstract: A semiconductor device includes a processing system including a section of power domain circuitry and a section of coin cell power domain circuitry. The coin cell power domain circuitry is configured to, when power is initially provided to the coin cell power domain circuitry, using power provided by a power management circuit as feedback to determine that the power management circuit provides the power in response to a power request signal being a toggle signal, and determine that the power management circuit provides the power in response to the power request signal being a pulse signal.Type: GrantFiled: July 31, 2013Date of Patent: September 6, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Lawrence L. Case, Matthew W. Brocker, Mingle Sun, Thomas E. Tkacik
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Patent number: 9424200Abstract: A run-time integrity checking (RTIC) method compatible with memory having at least portions that store data that is changed over time or at least portions configured as virtual memory is provided. For example, the method may comprise storing a table of page entries and accessing the table of page entries by, as an example, an operating system or, as another example, a hypervisor to perform RTIC on memory in which, as an example, an operating system, as another example, a hypervisor, or, as yet another example, application software is stored. The table may, for example, be stored in secure memory or in external memory. The page entry comprises a hash value for the page and a hash valid indicator indicating the validity status of the hash value. The page entry may further comprise a residency indicator indicating a residency status of the memory page.Type: GrantFiled: March 15, 2013Date of Patent: August 23, 2016Assignee: FREESCALE SEMICONDUCTOR, INC.Inventors: Thomas E. Tkacik, Matthew W. Brocker, Carlin R. Covey
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Patent number: 9418250Abstract: A system includes a tamper detector that includes a linear feedback shift register (LFSR) for generating pseudorandom coded detection signals as a function of seed values and a generator polynomial. The generator polynomial is loaded from a controller to the LFSR via software, and the seed values are directly loaded from a hardware-based random number generator to the LFSR. The tamper detector has output and input elements for connection to ends of a tamper detection circuit, wherein the detection circuit is linked with a physical closure surrounding an electronic circuit. The detection signals are applied to the output element and incoming signals are received from the tamper detection circuit at a comparator via the input element. Comparison of the incoming signals with the coded detection signals is performed to detect interference with the detection circuit in an attempt to tamper with the electronic circuit.Type: GrantFiled: July 23, 2014Date of Patent: August 16, 2016Assignee: Freescale Semiconductor, Inc.Inventor: Matthew W. Brocker
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Publication number: 20160026829Abstract: A system includes a tamper detector that includes a linear feedback shift register (LFSR) for generating pseudorandom coded detection signals as a function of seed values and a generator polynomial. The generator polynomial is loaded from a controller to the LFSR via software, and the seed values are directly loaded from a hardware-based random number generator to the LFSR. The tamper detector has output and input elements for connection to ends of a tamper detection circuit, wherein the detection circuit is linked with a physical closure surrounding an electronic circuit. The detection signals are applied to the output element and incoming signals are received from the tamper detection circuit at a comparator via the input element. Comparison of the incoming signals with the coded detection signals is performed to detect interference with the detection circuit in an attempt to tamper with the electronic circuit.Type: ApplicationFiled: July 23, 2014Publication date: January 28, 2016Inventor: Matthew W. Brocker
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Patent number: 9135129Abstract: A method and apparatus for testing operation of a random number generator (RNG) testing circuit are provided. In accordance with at least one embodiment, a first RNG output value obtained from a RNG is stored in a first register. In response to activation of a test mode to simulate a faulty RNG, the first RNG output value is stored in a second register. The first RNG output value in the first register is compared to the first RNG output value in the second register. In response to the comparing, a RNG failure signal is provided at a RNG testing circuit output of the RNG testing circuit. In accordance with at least one embodiment, sequential and combinational logic can simulate a faulty RNG. Accordingly, simulation of a faulty RNG may be performed to test a RNG testing circuit even when the RNG is not faulty.Type: GrantFiled: January 11, 2013Date of Patent: September 15, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Matthew W. Brocker, Steven E. Cornelius, Thomas E. Tkacik
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Patent number: 9092283Abstract: Methods and systems for producing random numbers include a random number generator with a first port and a second port. The first port is configured to receive a first type of random data request, and the random number generator is configured to generate first random data while the first type of request is asserted on the first port. The second port is configured to receive a second type of random data request, and the random number generator is configured to generate only a specified length of second random data in response to receiving the second type of request on the second port. An embodiment of a system also includes a data structure configured to store multiple random values, which are derived from the first random data generated by the random number generator in response to the first type of random data request.Type: GrantFiled: March 30, 2012Date of Patent: July 28, 2015Assignee: Freescale Semiconductor, Inc.Inventors: Thomas E. Tkacik, David G. Abdoo, Matthew W. Brocker, Steven D. Millman
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Publication number: 20150039916Abstract: A semiconductor device includes a processing system including a section of power domain circuitry and a section of coin cell power domain circuitry. The coin cell power domain circuitry is configured to, when power is initially provided to the coin cell power domain circuitry, using power provided by a power management circuit as feedback to determine that the power management circuit provides the power in response to a power request signal being a toggle signal, and determine that the power management circuit provides the power in response to the power request signal being a pulse signal.Type: ApplicationFiled: July 31, 2013Publication date: February 5, 2015Inventors: Lawrence L. Case, Matthew W. Brocker, Mingle Sun, Thomas E. Tkacik
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Patent number: 8856198Abstract: Embodiments of methods and systems for producing random values include a first module that provides a random data request (e.g., a request for an unspecified length of random data) to a random number generator. The random number generator generates random data in response to the random data request, and multiple random values derived from the random data are stored in a buffer. In response to receiving a request for a random value (e.g., an initialization vector), the first module produces the random value based on the multiple random values stored in the buffer. The system also may be configured to receive requests for other types of random values, and to fulfill those requests using random data that is not buffered (e.g., random data that is received directly from the random number generator in response to a request for a specified length of random data).Type: GrantFiled: March 30, 2012Date of Patent: October 7, 2014Assignee: Freescale Semiconductor, Inc.Inventors: David G. Abdoo, Matthew W. Brocker, Steven D. Millman, Thomas E. Tkacik
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Publication number: 20140281354Abstract: A run-time integrity checking (RTIC) method compatible with memory having at least portions that store data that is changed over time or at least portions configured as virtual memory is provided. For example, the method may comprise storing a table of page entries and accessing the table of page entries by, as an example, an operating system or, as another example, a hypervisor to perform RTIC on memory in which, as an example, an operating system, as another example, a hypervisor, or, as yet another example, application software is stored. The table may, for example, be stored in secure memory or in external memory. The page entry comprises a hash value for the page and a hash valid indicator indicating the validity status of the hash value. The page entry may further comprise a residency indicator indicating a residency status of the memory page.Type: ApplicationFiled: March 15, 2013Publication date: September 18, 2014Inventors: Thomas E. Tkacik, Matthew W. Brocker, Carlin R. Covey
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Publication number: 20140201252Abstract: A method and apparatus for testing operation of a random number generator (RNG) testing circuit are provided. In accordance with at least one embodiment, a first RNG output value obtained from a RNG is stored in a first register. In response to activation of a test mode to simulate a faulty RNG, the first RNG output value is stored in a second register. The first RNG output value in the first register is compared to the first RNG output value in the second register. In response to the comparing, a RNG failure signal is provided at a RNG testing circuit output of the RNG testing circuit. In accordance with at least one embodiment, sequential and combinational logic can simulate a faulty RNG. Accordingly, simulation of a faulty RNG may be performed to test a RNG testing circuit even when the RNG is not faulty.Type: ApplicationFiled: January 11, 2013Publication date: July 17, 2014Inventors: Matthew W. Brocker, Steven E. Cornelius, Thomas E. Tkacik
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Publication number: 20130262543Abstract: Embodiments of methods and systems for producing random values include a first module that provides a random data request (e.g., a request for an unspecified length of random data) to a random number generator. The random number generator generates random data in response to the random data request, and multiple random values derived from the random data are stored in a buffer. In response to receiving a request for a random value (e.g., an initialization vector), the first module produces the random value based on the multiple random values stored in the buffer. The system also may be configured to receive requests for other types of random values, and to fulfill those requests using random data that is not buffered (e.g., random data that is received directly from the random number generator in response to a request for a specified length of random data).Type: ApplicationFiled: March 30, 2012Publication date: October 3, 2013Inventors: DAVID G. ABDOO, Matthew W. Brocker, Steven D. Millman, Thomas E. Tkacik
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Publication number: 20130262542Abstract: Methods and systems for producing random numbers include a random number generator with a first port and a second port. The first port is configured to receive a first type of random data request, and the random number generator is configured to generate first random data while the first type of request is asserted on the first port. The second port is configured to receive a second type of random data request, and the random number generator is configured to generate only a specified length of second random data in response to receiving the second type of request on the second port. An embodiment of a system also includes a data structure configured to store multiple random values, which are derived from the first random data generated by the random number generator in response to the first type of random data request.Type: ApplicationFiled: March 30, 2012Publication date: October 3, 2013Inventors: THOMAS E. TKACIK, David G. Abdoo, Matthew W. Brocker, Steven D. Millman
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Patent number: 7512723Abstract: A queued interface device configured to communicate with a peripheral includes a first interface configured to receive and store a first set of peripheral requests from a first core, a second interface configured to receive and store a second set of peripheral requests from a second core, and an arbitrator coupled to the first interface and the second interface. The arbitrator, which may include multiple sets of registers to store the peripheral requests, is configured to selectively send the first set of peripheral requests and the second set of peripheral requests to the peripheral. The peripheral simultaneously appears as a dedicated peripheral for both the first and second cores.Type: GrantFiled: December 29, 2006Date of Patent: March 31, 2009Assignee: Freescale Semiconductor, Inc.Inventors: Thomas E. Tkacik, Matthew W. Brocker, Lawrence L. Case, Erik D. Swanson
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Publication number: 20080162745Abstract: A queued interface device configured to communicate with a peripheral includes a first interface configured to receive and store a first set of peripheral requests from a first core, a second interface configured to receive and store a second set of peripheral requests from a second core, and an arbitrator coupled to the first interface and the second interface. The arbitrator, which may include multiple sets of registers to store the peripheral requests, is configured to selectively send the first set of peripheral requests and the second set of peripheral requests to the peripheral. The peripheral simultaneously appears as a dedicated peripheral for both the first and second cores.Type: ApplicationFiled: December 29, 2006Publication date: July 3, 2008Inventors: Thomas E. Tkacik, Matthew W. Brocker, Lawrence L. Case, Erik D. Swanson
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Publication number: 20080028226Abstract: A system-on-a-chip and method for securely transferring data can include a trusted master; a first trusted slave; an untrusted component; and a common bus coupling the trusted master, the first trusted slave, and the untrusted component, In response to an initiation by a host, the trusted master provides a first access request to request a first data transfer with the first trusted slave, and wherein the trusted master does not perform the first data transfer until authentication of the first trusted slave.Type: ApplicationFiled: July 31, 2006Publication date: January 31, 2008Inventors: Matthew W. Brocker, Thomas E. Tkacik, James L. Johnson, Lawrence L. Case