Abstract: A comparator circuit having improved operational characteristics. A predetermined voltage drop device is provided, such as an exemplary embodiment Schottky diode, having an anode connected to circuit power supply voltage and an output stage of the comparator and a cathode connected to an input stage of the comparator. The predetermined voltage drop device effects a lowering of the power supply voltage for the output stage bias between said power supply voltage and said common voltage. This reduces the required swing of the output stage drivers during a comparator input signal transition and reduces propagation delay of said comparator.

Abstract: A resistance multiplier circuit coupled to a first node of a first circuit for providing a high-value resistance at the first node includes a first transistor, a second transistor being N times larger than the first transistor, and a resistor. In one embodiment, the first and second transistors are NPN bipolar transistors. The first transistor has its base and collector terminals coupled to the first node and an emitter terminal coupled to a second node. The second transistor has a base terminal coupled to the first node, a collector terminal coupled to a positive supply voltage, and an emitter terminal coupled to the second node. The resistor is coupled between the second node and a virtual ground node. When a voltage is applied to the first node, the resistance at the first node is (N+1) times the resistance of the resistor.

Abstract: A resistance multiplier circuit coupled to a first node of a first circuit for providing a high-value resistance at the first node includes a first transistor, a second transistor being N times larger than the first transistor, and a resistor. In one embodiment, the first and second transistors are NPN bipolar transistors. The first transistor has its base and collector terminals coupled to the first node and an emitter terminal coupled to a second node. The second transistor has a base terminal coupled to the first node, a collector terminal coupled to a positive supply voltage, and an emitter terminal coupled to the second node. The resistor is coupled between the second node and a virtual ground node. When a voltage is applied to the first node, the resistance at the first node is (N+1) times the resistance of the resistor.