Patents by Inventor Matthias Gries
Matthias Gries has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11829129Abstract: A method for generating an executable simulation program and simulating control device communication between a control device to be tested and at least one further control device includes: transferring a description of transmit and receive interfaces into a database; identifying interfaces of the control device to be tested; generating interfaces of the at least one further control device for each interface of the control device to be tested; storing the generated interface elements in the database; providing a configuration for the simulation of the control device communication between the control device to be tested and the at least one further control device; generating the executable simulation program; and simulating the control device communication.Type: GrantFiled: March 8, 2021Date of Patent: November 28, 2023Assignee: DSPACE GMBHInventor: Matthias Gries
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Publication number: 20230124300Abstract: The invention relates to a method for generating an executable simulation program and simulating control device communication (50) between a control device (10) to be tested and a further control device (20, 30, 40), the control device (10) to be tested having a description of its transmitting and receiving interfaces, and the method comprising the following steps: transferring the description of the transmitting and receiving interfaces to a database, identifying, by means of the database, the interfaces of the control device (10) to be tested from the description, generating a receiving interface element as a receiving interface of the one further control device for each identified transmitting interface of the control device to be tested, generating a transmitting interface element as a transmitting interface of the one further control device for each receiving interface of the control device to be tested, storing the generated interface elements (24, 26, 28, 34, 48) in the database, providing, by means ofType: ApplicationFiled: March 8, 2021Publication date: April 20, 2023Inventor: Matthias Gries
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Patent number: 9645938Abstract: In accordance with the present description, cache operations for a memory-sided cache in front of a backing memory such as a byte-addressable non-volatile memory, include combining at least two of a first operation, a second operation and a third operation, wherein the first operation includes evicting victim cache entries from the cache memory in accordance with a replacement policy which is biased to evict cache entries having clean cache lines over evicting cache entries having dirty cache lines. The second operation includes evicting victim cache entries from the primary cache memory to a victim cache memory of the cache memory, and the third operation includes translating memory location addresses to shuffle and spread the memory location addresses within an address range of the backing memory. It is believed that various combinations of these operations may provide improved operation of a memory. Other aspects are described herein.Type: GrantFiled: September 27, 2013Date of Patent: May 9, 2017Assignee: INTEL CORPORATIONInventors: Tim Kranich, Matthias Gries, Niklas Linkewitsch
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Patent number: 9513692Abstract: A memory controller operable for selective memory access to areas of memory exhibiting different attributes leverages different memory capabilities that vary access speed, retention time and power consumption, among others. Different areas of memory have different attributes while remaining available to applications as a single contiguous range of addressable memory. The memory controller employs an operating mode that identifies operational priorities for a computing device, such as speed, power conservation, or efficiency. The memory controller identifies an area of memory based on an expected usage of the data stored in the area, for example an access frequency indicating future retrieval. The memory controller therefore selects areas of memory based on the operating mode and the expected usage of data to be stored in the area according to a heuristic that favors areas of memory based on those exhibiting attributes having a high correspondence to the expected usage of the data.Type: GrantFiled: September 18, 2013Date of Patent: December 6, 2016Assignee: Intel CorporationInventors: Ruchir Saraswat, Matthias Gries, Nicholas P. Cowley
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Publication number: 20160203085Abstract: In accordance with the present description, cache operations for a memory-sided cache in front of a backing memory such as a byte-addressable non-volatile memory, include combining at least two of a first operation, a second operation and a third operation, wherein the first operation includes evicting victim cache entries from the cache memory in accordance with a replacement policy which is biased to evict cache entries having clean cache lines over evicting cache entries having dirty cache lines. The second operation includes evicting victim cache entries from the primary cache memory to a victim cache memory of the cache memory, and the third operation includes translating memory location addresses to shuffle and spread the memory location addresses within an address range of the backing memory. It is believed that various combinations of these operations may provide improved operation of a memory. Other aspects are described herein.Type: ApplicationFiled: September 27, 2013Publication date: July 14, 2016Inventors: Tim KRANICH, Matthias GRIES, Niklas LINKEWITSCH
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Patent number: 9335944Abstract: Methods and apparatus related to in-place change between transient and persistent state for data structures on non-volatile memory are described. In one embodiment, controller logic causes a change in a state of a first portion of one or more non-volatile memory devices between a persistent state and a transient state and without moving data stored in the first portion of the one or more non-volatile memory devices. Other embodiments are also disclosed and claimed.Type: GrantFiled: July 31, 2015Date of Patent: May 10, 2016Assignee: Intel CorporationInventors: Matthias Gries, Marcelo Cintra, Thomas Lehnig, Sebastian Steibl, Tor Lund-Larsen
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Publication number: 20160034224Abstract: Methods and apparatus related to in-place change between transient and persistent state for data structures on non-volatile memory are described. In one embodiment, controller logic causes a change in a state of a first portion of one or more non-volatile memory devices between a persistent state and a transient state and without moving data stored in the first portion of the one or more non-volatile memory devices. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: July 31, 2015Publication date: February 4, 2016Applicant: INTEL CORPORATIONInventors: Matthias Gries, Marcelo Cintra, Thomas Lehnig, Sebastian Steibl, Tor Lund-Larsen
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Patent number: 9195577Abstract: Dynamic operations for operations for 3D stacked memory using thermal data. An embodiment of a memory device includes memory having multiple coupled memory elements and multiple thermal sensors, including a first thermal sensor in a first area of the memory stack and a second thermal sensor in a second area of the memory stack. A memory controller is to provide operations to modify thermal conditions of the memory elements based at least in part on thermal information generated by the thermal sensors.Type: GrantFiled: September 30, 2011Date of Patent: November 24, 2015Assignee: Intel CorporationInventors: Ruchir Saraswat, Matthias Gries
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Patent number: 9128824Abstract: Methods and apparatus related to in-place change between transient and persistent state for data structures on non-volatile memory are described. In one embodiment, controller logic causes a change in a state of a first portion of one or more non-volatile memory devices between a persistent state and a transient state and without moving data stored in the first portion of the one or more non-volatile memory devices. Other embodiments are also disclosed and claimed.Type: GrantFiled: December 24, 2012Date of Patent: September 8, 2015Assignee: Intel CorporationInventors: Matthias Gries, Marcelo Cintra, Thomas Lehnig, Sebastian Steibl, Tor Lund-Larsen
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Patent number: 9026767Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.Type: GrantFiled: March 13, 2012Date of Patent: May 5, 2015Assignee: Intel CorporationInventors: Andre Schaefer, Matthias Gries
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Publication number: 20150082062Abstract: A memory controller operable for selective memory access to areas of memory exhibiting different attributes leverages different memory capabilities that vary access speed, retention time and power consumption, among others. Different areas of memory have different attributes while remaining available to applications as a single contiguous range of addressable memory. The memory controller employs an operating mode that identifies operational priorities for a computing device, such as speed, power conservation, or efficiency. The memory controller identifies an area of memory based on an expected usage of the data stored in the area, for example an access frequency indicating future retrieval. The memory controller therefore selects areas of memory based on the operating mode and the expected usage of data to be stored in the area according to a heuristic that favors areas of memory based on those exhibiting attributes having a high correspondence to the expected usage of the data.Type: ApplicationFiled: September 18, 2013Publication date: March 19, 2015Inventors: Ruchir Saraswat, Matthias Gries, Nicholas P. Cowley
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Publication number: 20140181367Abstract: Methods and apparatus related to in-place change between transient and persistent state for data structures on non-volatile memory are described. In one embodiment, controller logic causes a change in a state of a first portion of one or more non-volatile memory devices between a persistent state and a transient state and without moving data stored in the first portion of the one or more non-volatile memory devices. Other embodiments are also disclosed and claimed.Type: ApplicationFiled: December 24, 2012Publication date: June 26, 2014Inventors: Matthias Gries, Marcelo Cintra, Thomas Lehnig, Sebastian Steibl, Tor Lund-Larsen
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Patent number: 8737108Abstract: A 3D memory that is configurable for performance and power. An embodiment of a memory device includes a dynamic random-access memory (DRAM) including multiple memory dies, each memory die including multiple memory arrays, each memory array including peripheral logic circuits and a configurable logic. The memory device further includes a system element coupled with the DRAM, the system element including a memory controller. The memory controller is to provide for control of the configurable logic to provide for separate or shared peripheral logic circuits for one or more memory arrays, the configurable logic being configurable to enable or disable one or more of the peripheral logic circuits and to enable or disable one or more I/O connections between the memory arrays.Type: GrantFiled: September 25, 2012Date of Patent: May 27, 2014Assignee: Intel CorporationInventors: Ruchir Saraswat, Matthias Gries
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Publication number: 20140085959Abstract: A 3D memory that is configurable for performance and power. An embodiment of a memory device includes a dynamic random-access memory (DRAM) including multiple memory dies, each memory die including multiple memory arrays, each memory array including peripheral logic circuits and a configurable logic. The memory device further includes a system element coupled with the DRAM, the system element including a memory controller. The memory controller is to provide for control of the configurable logic to provide for separate or shared peripheral logic circuits for one or more memory arrays, the configurable logic being configurable to enable or disable one or more of the peripheral logic circuits and to enable or disable one or more I/O connections between the memory arrays.Type: ApplicationFiled: September 25, 2012Publication date: March 27, 2014Inventors: Ruchir Saraswat, Matthias Gries
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Publication number: 20130275665Abstract: Dynamic operations for operations for 3D stacked memory using thermal data. An embodiment of a memory device includes memory having multiple coupled memory elements and multiple thermal sensors, including a first thermal sensor in a first area of the memory stack and a second thermal sensor in a second area of the memory stack. A memory controller is to provide operations to modify thermal conditions of the memory elements based at least in part on thermal information generated by the thermal sensors.Type: ApplicationFiled: September 30, 2011Publication date: October 17, 2013Inventors: Ruchir Saraswat, Matthias Gries
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Publication number: 20130246734Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.Type: ApplicationFiled: March 13, 2012Publication date: September 19, 2013Inventors: Andre Schaefer, Matthias Gries
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Patent number: 8135936Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.Type: GrantFiled: December 23, 2009Date of Patent: March 13, 2012Assignee: Intel CorporationInventors: Andre Schaefer, Matthias Gries
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Publication number: 20110153908Abstract: A system monitors and dynamically changes memory mapping in a runtime of a computing system. The computing system has various memory resources, and multiple possible mappings that indicate how data is to be stored in and subsequently accessed from the memory resources. The performance of each memory mapping may be different under different runtime or load conditions of the computing device. A memory controller can monitor runtime performance of the current memory mapping and dynamically change memory mappings at runtime based on monitored or observed performance of the memory mappings. The performance monitoring can be modified for any of a number of different granularities possible within the system, from the byte level to memory channel.Type: ApplicationFiled: December 23, 2009Publication date: June 23, 2011Applicant: Intel CorporationInventors: Andre Schaefer, Matthias Gries
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Publication number: 20070113113Abstract: A data processing arrangement including a plurality of processing units. Each processing unit has a processing element, a data memory, a fill level unit, and a control unit. The processing element processes data stored in the data memory, or the data memory stores results of data processing performed by the processing element. The fill level unit generates a fill level signal signaling an amount of data stored in the data memory. The control unit controls processing power of the processing element based on the fill level signal.Type: ApplicationFiled: October 5, 2006Publication date: May 17, 2007Applicant: INFINEON TECHNOLOGIES AGInventors: Christian Sauer, Soeren Sonntag, Matthias Gries