Patents by Inventor Matthias Klemm

Matthias Klemm has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11952566
    Abstract: The invention relates to an apparatus 10 for storing and/or processing at least one medium 11, in particular a bioprocessing device, comprising at least one disposable container 1, which is designed to accommodate at least some of the at least one medium 11, and at least one overpressure protection means 5, which is fluid-connected to the at least one disposable container 1. The at least one overpressure protection means is designed, when triggered, to conduct at least some of the at least one medium 11 into an apparatus region 3a? in front of the overpressure protection means 5 in relation to a flow direction F, in particular into the at least one disposable container 1 and/or into at least one further, second container 1a.
    Type: Grant
    Filed: January 4, 2019
    Date of Patent: April 9, 2024
    Assignee: Sartorius Stedim Biotech GmbH
    Inventors: Bernhard Diel, Andreas Klemm, Matthias Hielscher, Alexandre Espachs, André Grebe
  • Patent number: 11920702
    Abstract: A connecting element for a pipe arrangement, comprising a base body with at least one through channel, a receiving bore for receiving a pipe end of a pipe, wherein the receiving bore corresponds with the through channel, wherein the receiving bore has a larger cross section than the through channel, wherein a transition step is introduced into the base body between the through channel and the receiving bore, and an arrangement and a method for manufacturing an arrangement.
    Type: Grant
    Filed: December 14, 2021
    Date of Patent: March 5, 2024
    Assignee: TI AUTOMOTIVE TECHNOLOGY CENTER GMBH
    Inventors: Jochen Klemm, Matthias Winter
  • Publication number: 20220289295
    Abstract: A motor vehicle includes a body which has a floor, where an open hollow profile is formed in the floor. The open hollow profile is bridged by the crossbeam. The crossbeam has at least one open hollow profile in a center region of the crossbeam, where a first outer profile section and a second outer profile section are integrally attached to the at least one open hollow profile in a transverse direction. The first outer profile section and the second outer profile section are spaced apart from one another by the at least one open hollow profile. The first outer profile section has a first rounded outer profile section and the second outer profile section has a second rounded outer profile section.
    Type: Application
    Filed: July 2, 2020
    Publication date: September 15, 2022
    Inventor: Matthias KLEMM
  • Patent number: 11255909
    Abstract: A method is disclosed for synchronizing a checking apparatus, in which the checking apparatus is configured for testing at least one first electronic closed-loop control unit. Further disclosed is a checking apparatus which is transferable to a synchronized state. Additionally disclosed is a composite system which includes at least two checking apparatuses. Also disclosed are a checking apparatus for testing at least one first closed-loop control unit, and a composite system including at least one checking apparatus and a further checking apparatus, the latter checking apparatus being configured to have the same effect as the first checking apparatus.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: February 22, 2022
    Assignee: DSPACE DIGITAL SIGNAL PROCESSING AND CONTROL ENGINEERING GMBH
    Inventors: Matthias Klemm, Daniel Baldin
  • Patent number: 11169208
    Abstract: A checking apparatus can test at least one first closed-loop control unit. The checking apparatus can include a first timing transmission unit which can generate a first periodic timing signal from a first time signal, and which can output the first periodic timing signal to a first PLL. The check device can further include a first oscillator which can generate a second periodic timing signal and which can output the second periodic timing signal to a second PLL. The checking device can additionally include a first clock, and can forward a first clock signal to a first input/output unit, and/or to a first computation unit. A first changeover signal can be used to control a first multiplexer such that depending on a state of the first changeover signal, the first multiplexer can forward either a first frequency-stabilized timing signal or a second frequency-stabilized timing signal to the first clock.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: November 9, 2021
    Assignee: DSPACE DIGITAL SIGNAL PROCESSING AND CONTROL ENGINEERING GMBH
    Inventor: Matthias Klemm
  • Patent number: 10331804
    Abstract: A system for testing at least a first automatic control device via a plant model includes: a first subsystem; and a second subsystem which is spatially separated from the first subsystem. The plant model comprises an executable first model code and an executable second model code. The first subsystem comprises a first time-signal processing component configured to electronically assign a first time signal (Ts1) from a global time source to a first event. The first model code is configured to provide a first calculation result based on the first event. The second subsystem comprises a second time-signal processing component configured to electronically assign a second time signal (Ts2) from the global time source to a second event. The second model code is configured to provide a second calculation result based on the second event.
    Type: Grant
    Filed: April 13, 2016
    Date of Patent: June 25, 2019
    Assignee: DSPACE DIGITAL SIGNAL PROCESSING AND CONTROL ENGINEERING GMBH
    Inventors: Andreas Himmler, Matthias Klemm
  • Publication number: 20190165996
    Abstract: A method for operating a real-time-capable simulation network having multiple network nodes for computing a simulation model. The network nodes are connected to one another via a serial data bus, and the network nodes exchange data via data bus messages. At least one event-driven task of the simulation model is implemented on a first network node, and a nondeterministic triggering event is detected by a second network node. The second network node communicates the detected triggering event to the first network node and the first network node computes the event-driven task. A fast response time is achieved by the means that a detection signal is sent from the second network node in the form of a multicast data bus message or a broadcast data bus message to multiple network nodes of the simulation network or to all network nodes of the simulation network over the serial data bus.
    Type: Application
    Filed: November 27, 2017
    Publication date: May 30, 2019
    Applicant: dSPACE digital signal processing and control engineering GmbH
    Inventors: Matthias KLEMM, Heiko KALTE, Robert POLNAU, Thorsten BREHM, Jochen SAUER, Hans-Juergen MIKS, Robert LEINFELLNER, Ruediger KRAFT, Magnus ASPLUND, Matthias SCHMITZ
  • Publication number: 20190146035
    Abstract: A method is disclosed for synchronizing a checking apparatus, in which the checking apparatus is configured for testing at least one first electronic closed-loop control unit. Further disclosed is a checking apparatus which is transferable to a synchronized state. Additionally disclosed is a composite system which includes at least two checking apparatuses. Also disclosed are a checking apparatus for testing at least one first closed-loop control unit, and a composite system including at least one checking apparatus and a further checking apparatus, the latter checking apparatus being configured to have the same effect as the first checking apparatus.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Inventors: Matthias KLEMM, Daniel BALDIN
  • Publication number: 20190107577
    Abstract: A checking apparatus can test at least one first closed-loop control unit. The checking apparatus can include a first timing transmission unit which can generate a first periodic timing signal from a first time signal, and which can output the first periodic timing signal to a first PLL. The check device can further include a first oscillator which can generate a second periodic timing signal and which can output the second periodic timing signal to a second PLL. The checking device can additionally include a first clock, and can forward a first clock signal to a first input/output unit, and/or to a first computation unit. A first changeover signal can be used to control a first multiplexer such that depending on a state of the first changeover signal, the first multiplexer can forward either a first frequency-stabilized timing signal or a second frequency-stabilized timing signal to the first clock.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 11, 2019
    Inventor: Matthias KLEMM
  • Patent number: 10180917
    Abstract: An interface unit for data exchange between a first processor of a computer system and a peripheral environment. The interface unit has a number of input data channels for receiving input data from the peripheral environment and a first access management unit. The access management unit is configured to receive a request for providing the input data, stored in the number of input data channels, from a first interface processor stored in the interface unit and from a second interface processor stored in the interface unit and to provide or not to provide the input data, stored in the number of input data channels, to the first interface processor and the second interface processor. A first priority and a second priority can be stored in the first access management unit.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: January 15, 2019
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Jochen Sauer, Robert Leinfellner, Matthias Klemm, Thorsten Brehm, Robert Polnau, Matthias Schmitz
  • Patent number: 10055363
    Abstract: A method for configuring an interface unit of a computer system with a first processor and a second processor stored in the interface unit. A data link is set up between the first processor and the second processor. A peripheral of the computer system is configured to store input data in an input data channel and to read output data from an output data channel, and the second processor is configured to read the input data from the input data channel and to store output data in the output data channel. A sequence of processor commands for the second processor is created such that a number of subsequences is created.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: August 21, 2018
    Assignee: dSPACE digital signal processing and control engineering GmbH
    Inventors: Jochen Sauer, Robert Leinfellner, Matthias Klemm, Thorsten Brehm, Robert Polnau, Matthias Schmitz
  • Publication number: 20160335101
    Abstract: A method for configuring an interface unit of a computer system with a first processor and a second processor stored in the interface unit. A data link is set up between the first processor and the second processor. A peripheral of the computer system is configured to store input data in an input data channel and to read output data from an output data channel, and the second processor is configured to read the input data from the input data channel and to store output data in the output data channel. A sequence of processor commands for the second processor is created such that a number of subsequences is created.
    Type: Application
    Filed: May 11, 2016
    Publication date: November 17, 2016
    Applicant: dSPACE digital signal processing and control engineering GmbH
    Inventors: Jochen SAUER, Robert LEINFELLNER, Matthias KLEMM, Thorsten BREHM, Robert POLNAU, Matthias SCHMITZ
  • Publication number: 20160335203
    Abstract: An interface unit for data exchange between a first processor of a computer system and a peripheral environment. The interface unit has a number of input data channels for receiving input data from the peripheral environment and a first access management unit. The access management unit is configured to receive a request for providing the input data, stored in the number of input data channels, from a first interface processor stored in the interface unit and from a second interface processor stored in the interface unit and to provide or not to provide the input data, stored in the number of input data channels, to the first interface processor and the second interface processor. A first priority and a second priority can be stored in the first access management unit.
    Type: Application
    Filed: May 11, 2016
    Publication date: November 17, 2016
    Applicant: dSPACE digital signal processing and control engineering GmbH
    Inventors: Jochen SAUER, Robert LEINFELLNER, Matthias KLEMM, Thorsten BREHM, Robert POLNAU, Matthias SCHMITZ
  • Publication number: 20160306900
    Abstract: A system for testing at least a first automatic control device via a plant model includes: a first subsystem; and a second subsystem which is spatially separated from the first subsystem. The plant model comprises an executable first model code and an executable second model code. The first subsystem comprises a first time-signal processing component configured to electronically assign a first time signal (Ts1) from a global time source to a first event. The first model code is configured to provide a first calculation result based on the first event. The second subsystem comprises a second time-signal processing component configured to electronically assign a second time signal (Ts2) from the global time source to a second event. The second model code is configured to provide a second calculation result based on the second event.
    Type: Application
    Filed: April 13, 2016
    Publication date: October 20, 2016
    Inventors: Andreas Himmler, Matthias Klemm
  • Patent number: 9181199
    Abstract: Disclosed are uracil derivatives of the formula (I): wherein R1, R2, R3, and X are as defined herein, and use thereof as therapeutic agents. The uracil derivatives are used in particular together with a cytostatic agent for suppressing or reducing resistance building up on cytostatic treatment.
    Type: Grant
    Filed: June 25, 2009
    Date of Patent: November 10, 2015
    Assignee: RESprotect GmbH
    Inventors: Rudolf Fahrig, Kurt Eger, Martin Fuhrer, Nicole Heinze, Matthias Klemm, Jorg-Christian Heinrich
  • Publication number: 20110166096
    Abstract: Disclosed are uracil derivatives of the formula (I): wherein R1, R2, R3, and X are as defined herein, and use thereof as therapeutic agents. The uracil derivatives are used in particular together with a cytostatic agent for suppressing or reducing resistance building up on cytostatic treatment.
    Type: Application
    Filed: June 25, 2009
    Publication date: July 7, 2011
    Applicant: RESPROTECT GMBH
    Inventors: Rudolf Fahrig, Kurt Eger, Martin Führer, Nicole Heinze, Matthias Klemm, Jörg-Christian Heinrich