Abstract: A method for structuring a silicon layer applies lacquer mask onto the silicon layer, and the silicon layer is selectively etched relative to the lacquer mask using an etching gas mixture comprising SF6, HBr and He/O2. The openings etched into the silicon layer with this method comprise especially steep sidewalls. Over and above this, the etching selectivity relative to a lacquer mask is clearly improved.

Abstract: The invention relates to a microelectronic structure which provides improved protection of a hydrogen-sensitive dielectric against hydrogen contamination. According to the invention, the hydrogen sensitive dielectric (14) is covered at lest by an intermediate oxide (18), where material thickness is at lest five times the thickness of the hydrogen-sensitive dielectric. The intermediate oxide (18) simultaneously acts as an internal dielectric and is metabolized on its surface for this purpose. The intermediate oxide (18), which has a sufficient thickness absorbers the hydrogen that may be released during the deposition of a hydrogen barrier layer (22, 26), thus protecting the hydrogen-sensitive dielectric (14).

Abstract: Method of fabricating an integrated memory device including the steps of providing a semiconductor substrate, including an array region and a support region; providing GC-lines in said array region and in said support region, wherein the GC-lines in said support region have a first height; providing in the array region bit line contacts projecting above said GC-lines, wherein said bit line contacts have a second height being higher than said first height; providing a first isolation layer, the maximum height of said GC-lines in said support region including the coverage of said first isolation layer being lower than said second height; providing a second isolation layer on said first isolation layer; and polishing said first isolation layer and said second isolation layer, such that a planar surface of the integrated memory device is provided and such that said bit line contacts are exposed.

Abstract: One (or more) contacts are produced on one or more active areas of a semiconductor wafer, it being possible for one or more isolated control lines to be arranged on the active areas with which contact is to be made. The control lines may, for example, be gate lines. The semiconductor component is fabricated in the following way: application of a polysilicon layer to the semiconductor wafer, patterning of the polysilicon layer, in order to produce a polysilicon contact above the active area, the polysilicon contact at least partly covering the two control lines, application of a first insulator layer to the semiconductor wafer, with the polysilicon contact being embedded, partial removal of the first insulator layer, so that at least the upper surface of the polysilicon contact is uncovered, and application of a metal layer to the semiconductor wafer in order to make electrical contact with the polysilicon contact.

Abstract: The invention provides a method for fabricating contact-making connections, having the steps of: a) providing a substrate (101) with electronic circuit units (102a, 102b) arranged thereon, an intermediate layer (103) filling an interspace between the electronic circuit units (102a, 102b); an insulation layer (104) being deposited on the electronic circuit units (102a, 102b) and on the intermediate layer (103); a masking layer (105) being deposited on the insulation layer (104); and the masking layer (105) being patterned with a through-plating structure (106); b) patterning a contact-making region by means of the masking layer (105), a contact-making hole (112) being etched through the insulation layer (104) and the intermediate layer (103) as far as the substrate (101), a section of the substrate (101) being uncovered in accordance with the through-plating structure (106); c) filling the contact-making hole (112) with a through-plating material (108); d) polishing back the covering layer (107) deposited on t

Abstract: A silicon dioxide layer is formed and a mask layer is deposited and then patterned to produce openings in the mask layer in the region around the gate contacts onto the gate electrode tracks in the logic region. The surface is uncovered around the gate contacts to the gate electrode tracks in the logic region, reducing the silicon dioxide layer. A sacrificial layer covering the gate electrode tracks is formed and patterned to form sacrificial layer blocks above the contact openings for the bit line contacts between the mutually adjacent gate electrode tracks in the cell array region and above the contact openings for the substrate contacts to the semiconductor surface and the gate contacts onto the gate electrode tracks in the logic region. A filling layer is formed between the sacrificial layer blocks, and the sacrificial layer blocks are removed. The contact opening regions are filled with conductive material.

Abstract: A hard mask made from polysilicon is used to etch a layer to be patterned. The hard mask is patterned using a resist mask. The etching of the hard mask is carried out in such a way that the openings which are etched into the hard mask have inclined sidewalls. This reduces the cross section of the openings, with the result that smaller openings can be formed in the layer that is to be patterned than the openings which have been predetermined by the resist mask. The hard mask is etched using only HBr. The inclination of the openings etched into the hard mask can be set by way of the TCP power and/or the bias power of a TCP etching chamber, and/or by way of the HBr flow rate.

Abstract: The invention provides a method for fabricating contact-making connections, having the steps of: a) providing a substrate (101) with electronic circuit units (102a, 102b) arranged thereon, an intermediate layer (103) filling an interspace between the electronic circuit units (102a, 102b); an insulation layer (104) being deposited on the electronic circuit units (102a, 102b) and on the intermediate layer (103); a masking layer (105) being deposited on the insulation layer (104); and the masking layer (105) being patterned with a through-plating structure (106); b) patterning a contact-making region by means of the masking layer (105), a contact-making hole (112) being etched through the insulation layer (104) and the intermediate layer (103) as far as the substrate (101), a section of the substrate (101) being uncovered in accordance with the through-plating structure (106); c) filling the contact-making hole (112) with a through-plating material (108); d) polishing back the covering layer (107) deposited on t

Abstract: Capacitor devices are formed in an essentially vertically extending fashion in order to achieve an essentially three-dimensional configuration or a configuration extending into the third dimension. A contacting of plug regions is performed after producing the capacitor devices. Such capacitor devices provide an increased integration density in a semiconductor memory device.

Abstract: A method of fabricating semiconductor memory devices is simplified by providing at least some plug regions, which are provided for contacting storage capacitor devices of a capacitor configuration, such that the plug regions have in each case a region that is elevated above the surface region of a passivation region.

Abstract: A method for producing a semiconductor structure includes applying at least one first layer, etching the first layer using a masking layer such that fences are produced, and, after removal of the masking layer and application of an auxiliary layer, the auxiliary layer and the fences are removed jointly except for a predetermined extent of the auxiliary layer. The present invention also relates to use of the method for producing spacers in a semiconductor structure.

Abstract: One (or more) contacts are produced on one or more active areas of a semiconductor wafer, it being possible for one or more isolated control lines to be arranged on the active areas with which contact is to be made. The control lines may, for example, be gate lines. The semiconductor component is fabricated in the following way. application of a polysilicon layer to the semiconductor wafer, patterning of the polysilicon layer, in order to produce a polysilicon contact above the active area, the polysilicon contact at least partly covering the two control lines, application of a first insulator layer to the semiconductor wafer, with the polysilicon contact being embedded, partial removal of the first insulator layer, so that at least the upper surface of the polysilicon contact is uncovered, and application of a metal layer to the semiconductor wafer in order to make electrical contact with the polysilicon contact.

Abstract: The invention relates to a microelectronic structure which provides improved protection of a hydrogen-sensitive dielectric against hydrogen contamination. According to the invention, the hydrogen sensitive dielectric (14) is covered at lest by an intermediate oxide (18), where material thickness is at lest five times the thickness of the hydrogen-sensitive dielectric. The intermediate oxide (18) simultaneously acts as an internal dielectric and is metabolized on its surface for this purpose. The intermediate oxide (18), which has a sufficient thickness absorbers the hydrogen that may be released during the deposition of a hydrogen barrier layer (22, 26), thus protecting the hydrogen-sensitive dielectric (14).

Abstract: To achieve a highest possible integration density in a semiconductor memory device having storage capacitors as storage elements, the method according to the invention forms the capacitor devices in substantially vertically extending fashion, to, as a result, achieve a substantially three-dimensional configuration and an configuration extending into the third dimension for the capacitor devices, a contact connection of the storage capacitors being formed after the production of the storage capacitors.

Abstract: To manufacture FeRAM memories in a particularly space-saving fashion and, thus, increase the storage density, a manufacturing method forms at least some of the multiplicity of capacitor devices used as storage elements with a multiplicity of individual capacitors that are connected in parallel with one another. The individual capacitors have ferroelectric or paraelectric dielectric regions with different coercitive voltages such that there is a resulting multiplicity of storage states for each of the individual capacitors.

Abstract: A method for structuring a silicon layer applies lacquer mask onto the silicon layer, and the silicon layer is selectively etched relative to the lacquer mask using an etching gas mixture comprising SF6, HBr and He/O2. The openings etched into the silicon layer with this method comprise especially steep sidewalls. Over and above this, the etching selectivity relative to a lacquer mask is clearly improved.

Abstract: A hard mask made from polysilicon is used to etch a layer to be patterned. The hard mask is patterned using a resist mask. The etching of the hard mask is carried out in such a way that the openings which are etched into the hard mask have inclined sidewalls. This reduces the cross section of the openings, with the result that smaller openings can be formed in the layer that is to be patterned than the openings which have been predetermined by the resist mask. The hard mask is etched using only HBr. The inclination of the openings etched into the hard mask can be set by way of the TCP power and/or the bias power of a TCP etching chamber, and/or by way of the HBr flow rate.

Abstract: A method for fabricating a capacitor configuration in particular an FeRAM memory device includes the step of filling intermediate regions, which remain free after the formation of a capacitor device on a surface of a substrate, with at least one electrically insulating intermediate layer. The at least one electrically insulating intermediate layer is filled at least up to a level of a topmost layer of the capacitor device.

Abstract: The integrated ferroelectric semiconductor memory is fabricated according to the stack cell principle. A ferroelectric capacitor module is formed on an intermediate oxide above a selection transistor located in or on a semiconductor wafer. The capacitor module is brought into conductive contact by its bottom capacitor electrode with an electrode of the selection transistor by means of an electrically conductive plug leading through the intermediate oxide. A layer system of a conductive oxygen diffusion barrier and a conductive adhesion layer is deposited directly below the bottom capacitor electrode, and the adhesion layer and the overlying oxygen diffusion barrier are deposited directly into the contact hole and form the plug at least in the region lying directly below the bottom capacitor electrode.

Abstract: Capacitor devices are formed in an essentially vertically extending fashion in order to achieve an essentially three-dimensional configuration or a configuration extending into the third dimension. A contacting of plug regions is performed after producing the capacitor devices. Such capacitor devices provide an increased integration density in a semiconductor memory device.