Abstract: Bonding wires for sophisticated bonding applications may be efficiently formed on the basis of a corresponding template device that may be formed on the basis of semiconductor material, such as silicon, in combination with associated fabrication techniques, such as lithography and etch techniques. Hence, any appropriate diameter and cross-sectional shape may be obtained with a high degree of accuracy and reliability.

Abstract: A new technique is disclosed in which a barrier/capping layer for a copper-based metal line is formed by using a thermal-chemical treatment with a surface modification on the basis of a silicon-containing precursor followed by an in situ plasma-based deposition of silicon nitride and/or silicon carbon nitride. The thermal-chemical treatment is performed on the basis of an ammonium/nitrogen mixture in the absence of any plasma ambient.

Abstract: By dividing a single chip area into individual sub-areas, a thermally induced stress in each of the sub-areas may be reduced during operation of complex integrated circuits, thereby enhancing the overall reliability of complex metallization systems comprising low-k dielectric materials or ULK material. Consequently, a high number of stacked metallization layers in combination with increased lateral dimensions of the semiconductor chip may be used compared to conventional strategies.

Abstract: The wire bond structure of sophisticated metallization systems, for instance based on copper, may be provided without a terminal aluminum layer and without any passivation layers for exposed copper surfaces by providing a fill material after the wire bonding process in order to encapsulate at least the sensitive metal surfaces and a portion of the bond wire. Hence, significant cost reduction, reduced cycle times and a reduction of the required process steps may be accomplished independently from the wire bond materials used. Thus, integrated circuits requiring a sophisticated metallization system may be connected by wire bonding to the corresponding package or carrier substrate with a required degree of reliability based on a corresponding fill material for encapsulating at least the sensitive metal surfaces.

Abstract: A conductive barrier material of a metallization system of a semiconductor device may be formed on the basis of one or more deposition/etch cycles, thereby providing a reduced material thickness in the bevel region, while enhancing overall thickness uniformity in the active region of the semiconductor substrate. In some illustrative embodiments, two or more deposition/etch cycles may be used, thereby providing the possibility to select reduced target values for the barrier thickness in the die regions, while also obtaining a significantly reduced thickness in the bevel region.

Abstract: A dielectric cap layer of a sophisticated metallization system may be provided in a locally restricted manner so as to enable direct contact of the dielectric material of one metallization layer with a low-k dielectric material of a subsequent metallization layer, which may thus provide enhanced adhesion and overall mechanical integrity.

Abstract: The invention relates to novel heteroaryl substituted acetone derivatives which inhibit the enzyme phospholipase A2, pharmaceutical preparations containing these compounds and a method of producing these compounds.

Abstract: In semiconductor devices having a copper-based metallization system, bond pads for wire bonding may be formed directly on copper surfaces, which may be covered by an appropriately designed protection layer to avoid unpredictable copper corrosion during the wire bond process. A thickness of the protection layer may be selected such that bonding through the layer may be accomplished, while also ensuring a desired high degree of integrity of the copper surface.

Abstract: A semiconductor device comprises metal lines in a specific metallization layer which have a different thickness and thus a different resistivity in different device regions. In this way, in high density areas of the device, metal lines of reduced thickness may be provided in order to comply with process requirements for achieving a minimum pitch between neighboring metal lines, while in other areas having less critical constraints with respect to minimum pitch, a reduced resistivity may be obtained at reduced lateral dimensions compared to conventional strategies. For this purpose, the dielectric material of the metallization layer may be appropriately patterned prior to forming respective trenches or the etch behavior of the dielectric material may be selectively adjusted in order to obtain differently deep trenches.

Abstract: By introducing a metallic species into an exposed surface area of a copper region, the electromigration behavior of this surface area may be significantly enhanced. The incorporation of the metallic species may be accomplished in a highly selective manner so as to not unduly affect dielectric material positioned adjacent to the metal region, thereby essentially avoiding undue increase of leakage currents.

Abstract: By directly forming an underbump metallization layer on a copper-based contact region, the formation of any other terminal metals, such as aluminum and corresponding adhesion/barrier layers may be avoided. Consequently, the thermal and electrical behavior of the resulting bump structure may be improved, while process complexity may significantly be reduced.

Abstract: In sophisticated semiconductor devices including copper-based metallization systems, a substantially aluminum-free bump structure in device regions and a substantially aluminum-free wire bond structure in test regions may be formed on the basis of a manufacturing process resulting in identical final dielectric layer stacks in these device areas. Moreover, reliable wire bond connections may be obtained by providing a protection layer, such as an oxide layer, after exposing the respective contact metal, such as copper, nickel and the like, thereby providing highly uniform process conditions during the subsequent wire bonding process. The number of process steps may be reduced by making a decision as to whether a substrate is to become a product substrate or test substrate for estimating the reliability of actual semiconductor devices. For example, nickel contact elements may be formed above copper-based contact areas wherein the nickel may provide a base for wire bonding or forming a bump material thereon.

Abstract: By performing a plasma treatment for efficiently sealing the surface of a stressed dielectric layer containing silicon nitride, an enhanced performance during the patterning of contact openings may be achieved, since nitrogen-induced resist poisoning may be significantly reduced during the selective patterning of stressed layers of different types of intrinsic stress.

Abstract: By forming a large metal pad and removing any excess material thereof, a pronounced recessed surface topography may be obtained, which may also affect the further formation of a metallization layer of a semiconductor device, thereby increasing the probability of maintaining metal residues above the recessed surface topography. Consequently, by providing test metal lines in the area of the recessed surface topography, the performance of a respective CMP process may be estimated with increased efficiency.

Abstract: In sophisticated semiconductor devices including copper-based metallization systems, a substantially aluminum-free bump structure in device regions and a substantially aluminum-free wire bond structure in test regions may be formed on the basis of a manufacturing process resulting in identical final dielectric layer stacks in these device areas. The number of process steps may be reduced by making a decision as to whether a substrate is to become a product substrate or test substrate for estimating the reliability of actual semiconductor devices. For example, nickel contact elements may be formed above copper-based contact areas wherein the nickel may provide a base for wire bonding or forming a bump material thereon.

Abstract: By measuring an electric characteristic of a test pad that is connected to a plurality of test vias formed in accordance with a specified process flow for forming contacts and vias of a semiconductor device, one or more process specific parameters may quantitatively be estimated. Thus, a fast and precise measurement method for contacts and vias is provided in a non-destructive manner.

Abstract: A new technique is disclosed in which a barrier/capping layer for a copper-based metal line is formed by using a thermal-chemical treatment followed by an in situ plasma-based deposition of silicon nitride and/or silicon carbon nitride. The thermal-chemical treatment is performed on the basis of an ammonium/nitrogen mixture in the absence of any plasma ambient.

Abstract: A manufacturing process of a semiconductor device includes generating a less random grain orientation distribution in metal features of a semiconductor device by employing a grain orientation layer. The less random grain orientation, e.g., a grain orientation distribution which has a higher percentage of grains that have a predetermined grain orientation, may lead to improved reliability of the metal features. The grain orientation layer may be deposited on the metal features wherein the desired grain structure of the metal features may be obtained by a subsequent annealing process, during which the metal feature is in contact with the grain orientation layer.

Abstract: By providing a barrier layer stack including a silicon nitride layer for confining a copper-based metal region, thereby also effectively avoiding any diffusion of oxygen and moisture into the copper region, and a nitrogen-enriched silicon carbide layer, the total relative permittivity may be maintained at a low level, since the thickness of the silicon nitride layer may be moderately thin, while the relatively thick silicon carbide nitride layer provides the required high etch selectivity during a subsequent patterning process of the low-k dielectric layer.

Abstract: By moderately introducing defects into a highly conductive material, such as copper, the resistance versus temperature behavior may be significantly modified so that enhanced electromigration behavior and/or electrical performance may be obtained in metallization structures of advanced semiconductor devices. The defect-related portion of the resistance may be moderately increased so as to change the slope of the resistance versus temperature curve, thereby allowing the incorporation of impurity atoms for enhancing the electromigration endurance while not unduly increasing the overall resistance at the operating temperature or even reducing the corresponding resistance at the specified operating temperature. Thus, by appropriately designing the electrical resistance for a target operating temperature, both the electromigration behavior and the electrical performance may be enhanced.