Patents by Inventor Matthieu Domonique Henri Pauly

Matthieu Domonique Henri Pauly has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10083269
    Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: September 25, 2018
    Assignee: ARM Limited
    Inventors: Paul De Dood, Marlin Wayne Frederick, Jerry Chaoyuan Wang, Brian Douglas Ngai Lee, Brian Tracy Cline, Xiaoqing Xu, Andy Wangkun Chen, Yew Keong Chong, Tom Shore, Sriram Thyagarajan, Gus Yeung, Yanbin Jiang, Emmanuel Jean Marie Olivier Pacaud, Matthieu Domonique Henri Pauly, Sylvia Xiuhui Li, Thanusree Achuthan, Daniel J. Albers, David William Granda
  • Publication number: 20180225402
    Abstract: A computer implemented system and method is provided for generating a layout of the cell defining a circuit component, the layout providing a layout pattern for a target process technology. The method comprises obtaining an archetype layout providing a valid layout pattern for the cell having regard to design rules of the target process technology, and receiving an input data file providing a process technology independent schematic of the circuit component for which the cell is to be generated. A schematic sizing operation is then performed on the input data file, having regard to both schematic constraints applicable to the target process technology and layout constraints derived from the archetype layout, in order to generate an output data file providing a process technology dependent schematic of the circuit component. A cell generation operation is then performed using the output data file and layout data determined from the archetype layout in order to generate the layout of the cell.
    Type: Application
    Filed: October 30, 2014
    Publication date: August 9, 2018
    Inventors: Paul DE DOOD, Marlin Wayne Frederick, JR., Jerry Chaoyuan Wang, Brian Douglas Ngai Lee, Brian Tracy Cline, Xiaoqing Xu, Andy Wangkun Chen, Yew Keong Chong, Tom Shore, Sriram Thyagarajan, Gus Yeung, Yanbin Jiang, Emmanuel Jean Marie Olivier Pacaud, Matthieu Domonique Henri Pauly, Sylvia Xiuhui Li, Thanusree Achuthan, Daniel J. Albers, David William Granda