Patents by Inventor Matti Tiikkainen
Matti Tiikkainen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11770237Abstract: A hardware accelerator is arranged to perform cipher operations and comprises a first memory area arranged to store a first bit string and a second memory area arranged to store a second bit string. A calculation block is arranged to receive a round key and to perform a function on the first bit string. The function comprises combining the first bit string with the round key to produce a combined bit string and performing a non-linear mapping from the combined bit string to a mapped bit string. An addition block is arranged to add the mapped bit string to the second bit string to produce a resultant bit string. A controller is arranged to receive a control signal and, depending on the state of the control signal, provides the first bit string and the resultant bit string to the appropriate memory area.Type: GrantFiled: June 12, 2019Date of Patent: September 26, 2023Assignee: Nordic Semiconductor ASAInventor: Matti Tiikkainen
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Patent number: 11386029Abstract: An electronic apparatus has a processor; a peripheral having a data interface and a data-attribute interface; a direct memory access (DMA) controller for the peripheral; a memory; a bus system connecting the processor, the DMA controller, and the memory; a data link between the DMA controller and the peripheral; and a data-attribute link between the DMA controller and the peripheral, separate from the data link. The DMA controller has data-transfer circuitry for transferring data between the memory and the data interface of the peripheral over the data link, and for transferring data-attribute information, associated with the data, between the memory and the data-attribute interface of the peripheral over the data-attribute link.Type: GrantFiled: May 28, 2019Date of Patent: July 12, 2022Assignee: Nordic Semiconductor ASAInventors: Marko Winblad, Markku Vähätaini, James Nevala, Matti Tiikkainen, Hannu Talvitie
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Patent number: 11387980Abstract: A hardware cipher engine encrypts or decrypts a block of input data from a sequence of blocks using a cipher operation where the block of output data depends on the input block's position in the sequence. In a random-access mode of operation, the engine receives a sequence position, receives a block of input data having that position, and outputs a block of output data without outputting data that encrypts, or that decrypts, every block of input data preceding the received position. In some embodiments, the operation is a stream cipher, and the engine generates a sequence of keystream blocks and performs a combining operation between the input block and a keystream block having a corresponding sequence position. In other embodiments, the cipher operation is a block cipher, and the engine generates, but doesn't output, blocks of data that encrypt, or decrypt, one or more blocks preceding the received input block.Type: GrantFiled: December 13, 2018Date of Patent: July 12, 2022Assignee: Nordic Semiconductor ASAInventors: Veli-Pekka Junttila, Harri Matomäki, James Nevala, Matti Tiikkainen, Markku Vähätaini, Marko Winblad
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Publication number: 20210216665Abstract: A hardware cryptographic engine comprises a direct-memory-access (DMA) input module for receiving input data over a memory bus, and a cryptographic module. The cryptographic module comprises an input register having an input-register length, and circuitry configured to perform a cryptographic operation on data in the input register. The hardware cryptographic engine further comprises an input-alignment buffer having a length that is less than twice said input-register length, and alignment circuitry performing an alignment operation on input data in the input-alignment buffer. The hardware cryptographic engine is configured to pass input data, received by the DMA input module, from the memory bus to the input register of the cryptographic module after buffering an amount of input data no greater than the length of the input-alignment buffer.Type: ApplicationFiled: May 29, 2019Publication date: July 15, 2021Applicant: Nordic Semiconductor ASAInventors: Marko WINBLAD, Markku VÄHÄTAINI, James NEVALA, Matti TIIKKAINEN, Hannu TALVITIE
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Publication number: 20210216482Abstract: An electronic apparatus has a processor; a peripheral having a data interface and a data-attribute interface; a direct memory access (DMA) controller for the peripheral; a memory; a bus system connecting the processor, the DMA controller, and the memory; a data link between the DMA controller and the peripheral; and a data-attribute link between the DMA controller and the peripheral, separate from the data link. The DMA controller has data-transfer circuitry for transferring data between the memory and the data interface of the peripheral over the data link, and for transferring data-attribute information, associated with the data, between the memory and the data-attribute interface of the peripheral over the data-attribute link.Type: ApplicationFiled: May 28, 2019Publication date: July 15, 2021Applicant: Nordic Semiconductor ASAInventors: Marko WINBLAD, Markku VÄHÄTAINI, James NEVALA, Matti TIIKKAINEN, Hannu TALVITIE
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Publication number: 20210160055Abstract: A hardware accelerator is arranged to perform cipher operations and comprises a first memory area arranged to store a first bit string and a second memory area arranged to store a second bit string. A calculation block is arranged to receive a round key and to perform a function on the first bit string. The function comprises combining the first bit string with the round key to produce a combined bit string and performing a non-linear mapping from the combined bit string to a mapped bit string. An addition block is arranged to add the mapped bit string to the second bit string to produce a resultant bit string. A controller is arranged to receive a control signal and, depending on the state of the control signal, provides the first bit string and the resultant bit string to the appropriate memory area.Type: ApplicationFiled: June 12, 2019Publication date: May 27, 2021Applicant: Nordic Semiconductor ASAInventor: Matti TIIKKAINEN
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Publication number: 20200313860Abstract: A hardware cipher engine encrypts or decrypts a block of input data from a sequence of blocks using a cipher operation where the block of output data depends on the input block's position in the sequence. In a random-access mode of operation, the engine receives a sequence position, receives a block of input data having that position, and outputs a block of output data without outputting data that encrypts, or that decrypts, every block of input data preceding the received position. In some embodiments, the operation is a stream cipher, and the engine generates a sequence of keystream blocks and performs a combining operation between the input block and a keystream block having a corresponding sequence position. In other embodiments, the cipher operation is a block cipher, and the engine generates, but doesn't output, blocks of data that encrypt, or decrypt, one or more blocks preceding the received input block.Type: ApplicationFiled: December 13, 2018Publication date: October 1, 2020Applicant: Nordic Semiconductor ASAInventors: Veli-Pekka JUNTTILA, Harri MATOMÄKI, James NEVALA, Matti TIIKKAINEN, Markku VÄHÄTAINI, Marko WINBLAD
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Publication number: 20060070994Abstract: A method and apparatus for packing, opening a soda can, for protecting the contents from contaminants during storage and shipping, the area on the container side covered by a cap being provided with an undercut zone, and elements being provided inside the twist-off cap for rupturing the undercut zone as the cap is rotated, the container presently beneath the cap opening along the undercut zone.Type: ApplicationFiled: October 3, 2005Publication date: April 6, 2006Inventor: Matti Tiikkainen