Abstract: A III-V compound planar HBT-FET device integrates field effect transistors (FETs) with heterojunction bipolar transistors (HBTs) formed on the same semiconductor substrate. An HBT fabricated on the substrate includes a collector, a base, and an emitter. The HBT emitter comprises a lightly doped layer of a first conductivity type deposited atop a heavily doped base layer of a second conductivity type, a lightly doped emitter cap layer of the first conductivity type deposited atop the emitter layer, and a heavily doped emitter contact layer of the first conductivity type deposited atop the emitter cap layer. A FET, isolated from the HBT by areas of ion implantation, is formed in the layers of material deposited during fabrication of the HBT. The FET has a source and a drain formed in the heavily doped emitter contact layer, a gate recess etched in the emitter contact layer between the source and drain, and a Schottky gate metal contact deposited on the lightly doped emitter cap layer exposed in the gate recess.

Abstract: A method of isolating individual heterojunction bipolar transistors (HBTs) on a wafer increases the current gain which can be obtained when using proton implantation to isolate the transistor. The photoresist pattern which is used to cover the transistor location during isolation implantation is undercut when etching the cap layer. A dielectric is then deposited on the etched surface, including the undercut portion. The photoresist is lifted off and an HBT is fabricated on the wafer in the area which is not covered by the dielectric. The dielectric on the undercut portion confines the emitter current to a region slightly removed from the isolation implant and provides improved current gain.

Abstract: A method for planarizing surfaces in multi-layered semiconductor structures using elevated features in the form of semiconductor materials, such as for forming heterojunctions, or interconnection metal. A process of forming the features includes leaving residual photoresist on the features. After feature formation and definition of transistor or other structure locations, dielectric material is deposited across the structure. Remaining photoresist is subsequently removed along with dielectric deposited thereon leaving dielectric between the features. A layer of polyimide is spun on the structure and into depressions between the dielectric and features. Typically material deposition, etching, dielectric backfilling and spin-coating steps are repeated until a predetermined number of contact or conductivity regions or interconnection metal layers are formed in the desired multi-layered structure.

Abstract: A heterostructure complementary transistor switch (HCTS) is fabricated using epitaxial layers on a substrate to form the desired P-N-P-N (or N-P-N-P) complementary structure in III-V compound semiconductor materials. Two HCTS are formed on a single substrate to form a memory cell. A collector and a base on one of the HCTs are connected to a base and a collector, respectively, on the other HCTS to form the memory cell.

Abstract: A dual lift-off technique is used to provide self-alignment of the emitter area, the emitter contact, and the base contact of a heterojunction, bipolar transistor. A photoresist pattern which defines an emitter adjacent a base contact is formed on a suitable heterojunction bipolar semiconductor wafer. A base contact is formed by etching through the first semiconductor to the heterojunction and depositing metal on the second semiconductor. Dielectric is then deposited on the base contact. The photoresist is then lifted off with its dual covering of dielectric and metal. The emitter contact metal can then be deposited without requiring critical alignment because the base contact is covered with dielectric.

Abstract: A method is disclosed which is capable of producing improved field effect transistors such as high electron mobility transistors and metal semiconductor field effect transistors. The method comprises a dual level photoresist deposition technique on a semiconductor wafer, in conjunction with a double lift-off and dummy gate procedure. In the process, T-bar shaped portions of overlying top and bottom photoresist layers are produced, one of such T-bar shaped portions forming a dummy gate. Metal is then deposited on the upper surface of the T-bar shaped portions and on the exposed surface of the substrate to form a source and a drain. In a first lift-off step the metal on the T-bar shaped portions and the underlying remaining top layer portions, are removed. An inorganic film such as SiO is then deposited on the remaining bottom layer portions and over the metal on the surface of the substrate.