Abstract: Dielectric conduits for the propagation of electromagnetic EHF signals include an elongate body of a dielectric material extending continuously along a longitudinal axis between a first terminus and a second terminus. At each point along the longitudinal axis, an orthogonal cross-section of the elongate body has a first dimension along a major axis of the cross-section, where the major axis extends along the largest dimension of the cross-section. The orthogonal cross-section also has a second dimension along a minor axis of the cross-section, where the minor axis extends along a widest dimension of the cross-section that is at a right angle to the major axis. For each cross-section of the elongate body, the first dimension is greater than the wavelength of the electromagnetic EHF signals and the second dimension is less than the wavelength of the electromagnetic EHF signals.

Abstract: Periodic near field directors (PNFD) are coupled to a transmitter and a receiver for a short-range millimeter wave wireless (M2W2) interconnect for transmitting and receiving radio frequency (RF) signals at millimeter-wave frequencies for short-range communication with high data rate capability between the transmitter and receiver. Each of the periodic near field directors is comprised of one or more periodic coupling structures (PSCs), wherein the periodic coupling structures are comprised of metallic strips positioned such that their lengthwise dimension is substantially perpendicular to a propagation direction of the radio frequency signals between the transmitter and receiver. Each of the periodic coupling structures is positioned parallel to adjacent periodic coupling structures with a separation distance between each periodic coupling structure being within one wavelength of the radio frequency signal.

Abstract: Low density parity check (LDPC) decoders are described utilizing a sequential schedule called Zigzag LBP (Z-LBP), for a layered belief propagation (LBP) architecture. Z-LBP has a lower computational complexity per iteration than variable-node-centric LBP (V-LBP), while being simpler than flooding and check-node-centric LBP (C-LBP). For QC-LDPC codes where the sub-matrices can have at most one “1” per column and one “1” per row, Z-LBP can perform partially-parallel decoding with the same performance as C-LBP. The decoder comprises a control circuit and memory coupled to a parity check matrix. Message passage is performed within Z-LBP in a first direction on odd iterations, and in a second direction on even iterations. As a result, a smaller parity check matrix can be utilized, while convergence can be more readily attained. The inventive method and apparatus can also be implemented for partially-parallel architectures.

Abstract: Interleaved three-dimensional (3D) on-chip differential inductors 110, 120 and transformer 100 are disclosed. The interleaved 3D on-chip differential inductors 110, 120 and transformer 100 make the best use of multiple metal layers in mainstream standard processes, such as CMOS, BiCMOS and SiGe technologies.

Abstract: A front-end module comprises a plurality of chips that includes first and second functional blocks and an interconnection circuit. The first functional block is formed using a first process type and includes a digital control circuit that generates a digital control signal in response to an external control signal from outside the front end module. The second functional block is formed using a second process type and includes a digitally controlled circuit controlled by the digital control signal generated by the first functional block. The second process type is different from the first process type. The interconnection circuit couples the digital control circuit and the digitally controlled circuit to provide the digital control signal to the digitally controlled circuit. In one aspect, the first functional block may be a low noise amplifier formed by a pseudomorphic high electron mobility transistor process.

Abstract: A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit includes a digital-to-analog differentiator. The digital-to-analog differentiator may be, for example, a single-bit first-order digital-to-analog differentiator, a single-bit second-order digital-to-analog differentiator, or a full M-bit binary-weighted digital to analog differentiator.

Abstract: Tuning devices and methods are disclosed. One of the devices comprises a metal structure connected with artificial dielectric elements, and variable capacitance devices. Each variable capacitance device is connected with a respective artificial dielectric element and with a control signal. Control of the variation of the capacitance allows the desired tuning. Another device comprises metallic structures connected with artificial dielectric elements and switches connected between the artificial dielectric elements. Turning ON and OFF the switches allows the capacitance between artificial dielectric elements to be varied and a signal guided by the metallic structures to be tuned.

Abstract: A millimeter wave wireless (M2W2) interconnect is used for transmitting and receiving signals at millimeter-wave frequencies for short-range wireless communication with high data rate capability. The transmitter and receiver antennae may comprise an on-chip differential dipole antenna or a bond wire differential dipole antenna. The bond wire differential dipole antenna is comprised of a pair of bond wires connecting between a pair of pads on an integrated circuit (IC) die and a pair of floating pads on a printed circuit board (PCB).

Abstract: Generation of Terahertz range (300 GHz to 3 THz) frequencies is increasingly important for communication, imaging and spectroscopic systems, including concealed object detection. Apparatus and methods describe generating multiple phase signals which are phase-locked at a fundamental frequency, which are then interleaved into an output which is a multiple of the fundamental frequency. By way of example phase generators comprise cross-coupling transistors (e.g., NMOS) and twist coupling transistors (NMOS) for generating a desired number of phase-locked output phases. A rectifying interleaver comprising a transconductance stage and Class B amplifiers provides superimposition of the phases into an output signal. The invention allows frequency output to exceed the maximum frequency of oscillation of a given device technology, such as CMOS in which a 324 GHz VCO in 90 nm digital CMOS with 4 GHz tuning was realized.

Abstract: A Self-Synchronized Radio Frequency RF-Interconnect (SSRFI), based on capacitor coupling and peak detection, for vertically interconnecting active device layers in three-dimensional (3D) integrated circuits (IC), as well as wireless communication and RF signal transmission/receiving.

Abstract: A step gain amplifier has an amplifier with an input and an output, and a bias circuit connected to the input and to a bias node. A passive feedback circuit using only passive elements connects the output to the input. A control circuit is connected to the bias circuit at the bias node.

Abstract: A phase lock loop includes a quantization circuit that generators an out of phase noise cancellation signal from an error in a delta-sigma modulator and applies the noise cancellation signal to the charge pump. The quantization circuit includes a digital-to-analog differentiator. The digital-to-analog differentiator may be, for example, a single-bit first-order digital-to-analog differentiator, a single-bit second-order digital-to-analog differentiator, or a full M-bit binary-weighted digital to analog differentiator.

Abstract: The present disclosure relates to coupled circuits and methods of coupling circuits having a power supply wherein a plurality of transistors are inductively coupled directly to the power supply for providing a single DC supply voltage directly to each of the plurality of transistors, and wherein a plurality of transformers have primary and secondary windings, the primary and secondary windings providing, at least in part, inductive loads for inductively coupling the plurality of transistors to the power supply, the plurality of transformers also providing an AC signal path for coupling neighboring ones of the plurality of transistors together.

Abstract: Phase-coherent differential structures contain a phase-coherent transformer having two pairs of phase-coherent coupled differential inductors.

Abstract: Low density parity check (LDPC) decoders are described utilizing a sequential schedule called Zigzag LBP (Z-LBP), for a layered belief propagation (LBP) architecture. Z-LBP has a lower computational complexity per iteration than variable-node-centric LBP (V-LBP), while being simpler than flooding and check-node-centric LBP (C-LBP). For QC-LDPC codes where the sub-matrices can have at most one “1” per column and one “1” per row, Z-LBP can perform partially-parallel decoding with the same performance as C-LBP. The decoder comprises a control circuit and memory coupled to a parity check matrix. Message passage is performed within Z-LBP in a first direction on odd iterations, and in a second direction on even iterations. As a result, a smaller parity check matrix can be utilized, while convergence can be more readily attained. The inventive method and apparatus can also be implemented for partially-parallel architectures.

Abstract: A step gain amplifier has an amplifier with an input and an output, and a bias circuit connected to the input and to a bias node. A passive feedback circuit using only passive elements connects the output to the input. A control circuit is connected to the bias circuit at the bias node.

Abstract: Systems and methods are disclosed for wireless transmission and reception of data including processing and buffering features. According to one or more exemplary aspects, there is provided a wireless audio receiver for receiving a plurality of packets of encoded audio data. Moreover, the receiver includes at least one receiving component that receives the plurality of packets to generate a plurality of decoded signals, a decoding component that decodes the first packet of encoded data transmitted to produce decoded data, and a selecting component that identifies the mechanisms for receiving additional encoded data. Other exemplary embodiments may include one or more receiving components that processing data regarding antenna, frequencies and channels selected for transmission, as well as an audio component that receives the decoded signals and produces decoded audio signals.

Abstract: An attenuator system comprises an attenuator and a control circuit for controlling the attenuation of the attenuator. In one embodiment, the attenuator comprises two diodes or two diode connected transistors, and the control circuit comprises two transistors as the only active devices. In another embodiment, the control circuit comprises another transistor in a shut down circuit.

Abstract: Tuning devices and methods are disclosed. One of the devices comprises a metal structure connected with artificial dielectric elements, and variable capacitance devices. Each variable capacitance device is connected with a respective artificial dielectric element and with a control signal. Control of the variation of the capacitance allows the desired tuning. Another device comprises metallic structures connected with artificial dielectric elements and switches connected between the artificial dielectric elements. Turning ON and OFF the switches allows the capacitance between artificial dielectric elements to be varied and a signal guided by the metallic structures to be tuned.

Abstract: An amplifier circuit comprises a detection power input circuit for receiving an RF signal, and a bias circuit that includes an output for generating a bias signal in response to a reference control voltage. The power detector further comprises a detection circuit for generating a power control voltage having a voltage characteristic that offsets temperature characteristics of the received RF signal. The amplifier circuit further comprises a power amplifier coupled to the bias circuit. The power amplifier includes a driver stage providing the RF signal. The detection circuit compensates temperature variation of the inputted detection voltage of the received RF signal.