Abstract: A self-contained method and structure for partitioning, testing and diagnosing a multi-chip packaging structure. The method comprises the steps of electronically inhibiting all chips in the multi-chip package except for the chip or chips under test, creating a signature of the chip or chips under test by generating and applying random patterns to the chip or chips under test (referred to as the unit under test) and comparing the signature obtained to a "good machine" simulation signature. The structure comprises means for accomplishing the above method steps. A preferred structure comprises an semiconductor substrate having redundant self test circuitry built in and chips having ECIPT circuitry mounted on the semiconductor substrate. Either all or a portion of the self test circuitry, including the required multiplexers, etc., may be incorporated into the semiconductor substrate. ECIPT circuitry may also be built into the substrate below each chip site.

Abstract: The disclosure is directed to an electronically selectable redundant array or memory technique and circuitry. More particularly the invention utilizes Level Sensitive Scan Design (LSSD) circuitry with limited modification to perform the additional function of selecting a redundant word (or words) in a memory chip containing at least one defective word. The correction mechanism is independent of which word line (or word lines) is bad, and is therefore independent of I/O pin (or pad) connection of the array chip.

Abstract: This specification deals with testing of a network of electrical interconnections between chips mounted on an insulative substrate of a module and between the chips and the input and output pins of the module. Each of the mounted chips contains masking circuits which can be activated to prevent controlling signals from the outputs of logic circuits on the chip from being transmitted off the chip and into the interconnection network. Also each of the chips contains emitter follower circuits that logically connect all the chip input terminals to a common output terminal of the chip. In testing the mask circuits are activated. Then potential levels are selectively applied to a plurality of test points in the interconnection network and differences in potential level between these test points and/or between the points and one or more of the common terminals are determined.