Abstract: A low-consumption and high-density D flip-flop circuit implementation, particularly for standard cell libraries, which comprises a master section and a slave section, is disclosed and claimed. The master section includes a master latch structure, a master coupling circuit which connects the master latch structure to one of two supply voltages, and an input coupling circuit for applying data to the flip-flop. The slave section includes a slave latch structure directly interposed between two supply voltages, and a slave coupling circuit which connects the slave latch structure to the master latch structure. The number of transistors required to realize the D flip-flop circuit implementation of the invention is minimized by enlarging the source areas of transistors in the input coupling circuit, which results in a large stray capacitance and insures optimum operation of the master latch. In addition, transistors in the slave latch structure have non-minimal gate lengths.

Abstract: The bias and precharging circuit comprises a bias part and a precharging part of the bit line together with a sensing amplifier operating by comparison of the voltage of the bit line and a dummy bit line. The precharging part includes components which turn off the bias and precharging parts as soon as the sensing amplifier has read the cell subjected to precharging. The bias part includes components for amplifying the voltage unbalance produced by bias between the bit line and the dummy bit line. It provides a current-mirror to cause said voltage unbalance independently of the precharging part.

Abstract: The device comprises a first chain of scanning cells located at the stimulation input of each respective functional block of the integrated circuit and a second chain of scanning cells located at the assessment output of each respective functional block of the integrated circuit. Each cell comprises a master part, a slave part and switching circuit to alternately enable the master and slave parts under the control of respective master clock and slave clock signals coincident with opposite phases of a scanning clock signal having a substantially square wave. With each pair of chains of scanning cells there are associated clock generators to locally obtain the master and slave clocks from the scanning clock.

Abstract: The circuit comprises a first switching circuit which receives at an input a system clock normally provided for the operation of the integrated circuit and produces at an output a machine clock normally coincident with the system clock, circuitry for clamping the first switching circuit responsive to a firing signal of the serial operational analysis device determines which state the machine clock is clamped in and second switching circuit which receives at an input the system clock and is responsive to the firing signal to produce a scanning clock which repeats the system clock in an inverted or non-inverted manner according to the state in which the machine clock has been clamped.

Abstract: Two P channel selection transistors are inserted in respective connecting circuit branches between two external pins with voltages Vcc and Vpp respectively and an internal node. A switching circuit controls said selection transistors. Circuit means are provided to hold the body bias of the selection transistors at a voltage equal to the highest voltage present from time to time at said external pins.

Abstract: The power-on reset circuit is adapted to automatically provide a voltage pulse as a positive supply voltage is applied.

Abstract: A bootstrap condenser connected to the output of the circuit is preloaded during the low output state when the load transistor is off and the drive transistor is normally on. A commutation signal brings about extinction of the drive transistor and connection of the condenser to the gate of the load transistor to turn on the latter and secure the resulting rise of the circuit output. Transistors of the pilot circuit are arranged for maximum bootstrap efficiency.

Abstract: An integrated structure composed of a processing unit (CPU), ROM memory, RAM memory and other optional functions, such as input/output etc., is arranged as a microcomputer, in which all or part of the RAM is a non-volatile memory which carries out during normal operation all the functions of a RAM while also being able, through suitable circuit structures, to store in a permanent (non-volatile) way the data contained therein, retaining the data when the power feed to the circuit is cut off, and recalling the same data at power turn-on.The structure provides for the handling of the non-volatile memory in its different functions, and its arrangement and compatibility with the processing unit, through suitable circuitry and control signals.

Abstract: The circuit comprises a first switching circuit which receives at an input a system clock normally provided for the operation of the integrated circuit and produces at an output a machine clock normally coincident with the system clock, circuitry for clamping the first switching circuit responsive to a firing signal of the serial operational analysis device determines which state the machine clock is clamped in and second switching circuit which receives at an input the system clock and is responsive to the firing signal to produce a scanning clock which repeats the system clock in an inverted or non-inverted manner according to the state in which the machine clock has been clamped.

Abstract: The device comprises a first chain of scanning cells located at the stimulation input of each respective functional block of the integrated circuit and a second chain of scanning cells located at the assessment output of each respective functional block of the integrated circuit. Each cell comprises a master part, a slave part and switching circuit to alternately enable the master and slave parts under the control of respective master clock and slave clock signals coincident with opposite phases of a scanning clock signal having a substantially square wave. With each pair of chains of scanning cells there are associated clock generators to locally obtain the master and slave clocks from the scanning clock.