Patents by Inventor Mauro Bonanomi
Mauro Bonanomi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9454427Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.Type: GrantFiled: September 15, 2015Date of Patent: September 27, 2016Assignee: MICRON TECHNOLOGY, INC.Inventors: Aswin Thiruvengadam, Angelo Visconti, Mauro Bonanomi, Richard E. Fackenthal, William Melton
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Publication number: 20160004595Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.Type: ApplicationFiled: September 15, 2015Publication date: January 7, 2016Inventors: Aswin Thiruvengadam, Angelo Visconti, Mauro Bonanomi, Richard E. Fackenthal, William Melton
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Patent number: 9176831Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.Type: GrantFiled: February 2, 2015Date of Patent: November 3, 2015Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, Angelo Visconti, Mauro Bonanomi, Richard E. Fackenthal, William Melton
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Publication number: 20150149838Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.Type: ApplicationFiled: February 2, 2015Publication date: May 28, 2015Inventors: Aswin Thiruvengadam, Angelo Visconti, Mauro Bonanomi, Richard E. Fackenthal, William Melton
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Patent number: 8977929Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.Type: GrantFiled: February 27, 2013Date of Patent: March 10, 2015Assignee: Micron Technology, Inc.Inventors: Aswin Thiruvengadam, Angelo Visconti, Mauro Bonanomi, Richard E. Fackenthal, William Melton
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Publication number: 20140245107Abstract: This disclosure relates to avoiding a hard error in memory during write time by shifting data to be programmed to memory to mask the hard error. In one implementation, a method of programming data to a memory array includes obtaining error data corresponding to a selected memory cell, shifting a data pattern such that a value to be stored by the selected memory cell matches a value associated with a hard error, and programming the shifted data pattern to memory array such that the value programmed to the selected memory cell matches the value associated with the hard error.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: MICRON TECHNOLOGY, INC.Inventors: Aswin Thiruvengadam, Angelo Visconti, Mauro Bonanomi, Richard E. Fackenthal, William Melton
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Patent number: 8791418Abstract: A two-dimensional array of memory cells may be used to implement a spatial dosimeter. The two-dimensional array of cells may be implemented by an integrated circuit memory. Because of the relatively small size of the integrated circuit memory, the resolution of the resulting array may be less than 100 nanometers. The change in threshold voltage of each of the cells, as a result of radiation exposure, may be used to calculate the dose seen at each cell, allowing dose profiles in two dimensions with sub-micrometer resolution.Type: GrantFiled: December 8, 2008Date of Patent: July 29, 2014Assignee: Micron Technology, Inc.Inventors: Angelo Visconti, Mauro Bonanomi, Giorgio Cellere, Alessandro Paccagnella
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Publication number: 20100140488Abstract: A two-dimensional array of memory cells may be used to implement a spatial dosimeter. The two-dimensional array of cells may be implemented by an integrated circuit memory Because of the relatively small size of the integrated circuit memory, the resolution of the resulting array may be less than 100 nanometers. The change in threshold voltage of each of the cells, as a result of radiation exposure, may be used to calculate the dose seen at each cell, allowing dose profiles in two dimensions with sub-micrometer resolution.Type: ApplicationFiled: December 8, 2008Publication date: June 10, 2010Inventors: Angelo Visconti, Mauro Bonanomi, Giorgio Cellere, Alessandro Paccagnella
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Patent number: 7471571Abstract: A method programs a memory device that includes at least one memory cell matrix. The programming method the steps of: erasing the memory cells; soft programming the memory cells; and complete programming of a group of such memory cells each of them storing its own logic value. Advantageously, the first complete programming step of a group of such memory cells involves cells belonging to a block (A) of the matrix being electrically insulated from the rest of the matrix. A memory device suitable to implement the proposed method is also described.Type: GrantFiled: February 6, 2006Date of Patent: December 30, 2008Inventors: Angelo Visconti, Mauro Bonanomi
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Patent number: 7285816Abstract: A CAM memory cell integrated on a semiconductor substrate includes a plurality of floating gate memory cells, matrix-organized in rows, called word lines, and columns, called bit lines. The cells belonging to a same row and have floating gate electrodes are short-circuited with each other in order to form a single floating gate electrode for the CAM memory cell. Advantageously, the single floating gate electrode is equipped with at least a cavity manufactured in at least a side wall of the single floating gate electrode. A process for manufacturing CAM memory cells integrated on a semiconductor substrate is also described.Type: GrantFiled: August 26, 2004Date of Patent: October 23, 2007Assignee: STMicroelectronics S.r.l.Inventor: Mauro Bonanomi
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Publication number: 20070211534Abstract: The method for programming/erasing a non volatile memory cell device includes at least one electric stress step to apply, to at least one active oxide layer of at least one memory cell of the device, a stress electric field able to remove at least a part of charges trapped in the active oxide layer. The method may be used for devices with floating gate type memory cells. The electric stress step may include the application, to one or more terminals of at least one memory cell, of potentials able to produce an electric field on a corresponding active oxide layer.Type: ApplicationFiled: March 9, 2007Publication date: September 13, 2007Applicant: STMicroelectronics S.r.l.Inventors: Angelo Visconti, Mauro Bonanomi, Daniele Ielmini, Alessandro Spinelli
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Publication number: 20060203544Abstract: A method programs a memory device that includes at least one memory cell matrix. The programming method the steps of: erasing the memory cells; soft programming the memory cells; and complete programming of a group of such memory cells each of them storing its own logic value. Advantageously, the first complete programming step of a group of such memory cells involves cells belonging to a block (A) of the matrix being electrically insulated from the rest of the matrix. A memory device suitable to implement the proposed method is also described.Type: ApplicationFiled: February 6, 2006Publication date: September 14, 2006Applicant: STMicroelectronics S.r.l.Inventors: Angelo Visconti, Mauro Bonanomi
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Publication number: 20050230739Abstract: A CAM memory cellintegrated on a semiconductor substrateincludes a plurality of floating gate memory cells, matrix-organized in rows, called word lines, and columns, called bit lines. The cells belonging to a same row and have floating gate electrodes are short-circuited with each other in order to form a single floating gate electrodefor the CAM memory cell. Advantageously, the single floating gate electrodeis equipped with at least a cavity manufactured in at least a side wall of the single floating gate electrode. A process for manufacturing CAM memory cellsintegrated on a semiconductor substrateis also described.Type: ApplicationFiled: August 26, 2004Publication date: October 20, 2005Applicant: STMicroelectronics S.r.l.Inventor: Mauro Bonanomi