Abstract: Techniques are disclosed for eliminating redundancy in fault simulations to improve efficiency and to reduce the time and computing power required to generate a robust fault list, which results in adequate diagnostic coverage of a particular post-silicon electronic device for functional safety applications. The techniques described herein implement an automated methodology to identify identical sub-circuits in a design after the design is synthesized to gates, and utilize isomorphism to define a manner in which identical blocks may be reliably identified to ensure adequate coverage and accurate, consistent fault injection results. The netlist may advantageously implement a “flat” as opposed to a hierarchal design. Moreover, multiple levels of granularity may be identified for the various sub-circuits associated with the reference graphs used to identify isomorphic sub-graphs.

Abstract: Methods, systems and apparatuses may provide for technology that applies a functional safety test stimulus to a hardware level simulator, automatically compiles an output of the hardware level simulator into a software test library (STL), and iteratively verifies that the diagnostic coverage of the STL file approximates the diagnostic coverage of the functional safety test stimulus.

Abstract: Methods, systems and apparatuses may provide for technology that applies a functional safety test stimulus to a hardware level simulator, automatically compiles an output of the hardware level simulator into a software test library (STL), and iteratively verifies that the diagnostic coverage of the STL file approximates the diagnostic coverage of the functional safety test stimulus.

Abstract: A method to perform a hybrid Register Transfer Level (RTL)/gate-level (GL) fault injection simulation of a hardware design comprises generating a list of one or more fault nodes in a GL netlist for the hardware design, mapping functionally equivalent comparison points between RTL logic for the hardware design and GL netlist of the hardware design, identifying a nearest set of downstream comparison points for one or more logic paths for the one or more fault nodes, identifying a nearest set of upstream comparison points for the one or more identified downstream comparison points, replacing RTL logic with equivalent GL netlist logic to provide hybrid RTL/GL netlist in code, and performing fault injection simulating using the hybrid RTL/GL netlist code