Abstract: A semiconductor probe card having a plurality of micromachined probes tips for contacting an array of electrode pads formed on a semiconductor integrated circuit is provided. The plurality of probe tips are formed on the top surface of the substrate wherein the probe tips are arranged in an array matching of electrode pads on the integrated circuit to be tested. A portion of the semiconductor substrate underneath the probe tips is thin, so that the probe tips rests on a flexible diaphragm or beam.

Abstract: An antimetastable state circuit which detects when a data edge is so close to a clock edge that it would result in a metastable state in a time measurement circuit is provided. When a potential metastable state is detected, the antimetastable circuit delays the data edge with respect to the clock edge by a known amount so as to avoid the metastable state. The delayed edge is used to start the time measurement circuit, and the next clock edge is used to stop the time measurement circuit. When the known delay has been added, it is subtracted from the measured time, to produce an accurate measurement of the elapsed time between the rise of the data edge and the rise of the clock edge.

Abstract: The present invention relates, in general, to an electronic and measuirng circuits are located remotely from the test head. A low device count circuit at each pin performs the necessary high speed switching. The force and measure lines are relatively long, but the signal rates are low enough to be accurately transmitted. The only high rate signals are on lines coupled to the gates of FET switches at the test head. Thus, multiple pin, high speed testing can be accomplished using relatively small and inexpensive test heads.

Abstract: An automated integrated circuit tester is constructed as a state machine. Complete test routines are contained in a state memory. A state generator is controlled by state memory and produces addresses therefor. A complete test condition can be set up using the information in a single address in state memory. Provisions are made for test routine loading from a local computer, which also serves to log data without interfering in test execution. A preferred embodiment provides both DC parametric and AC testing in a tester which can accomodate up to 256 pins. A single force and measure unit is devoted to each pin.