Abstract: A method of fabricating self-aligned static induction transistors is disclosed. The method comprises fabricating a silicon substrate having an active area. A guard ring is formed around the active area. Source and gate regions are formed, and a self-aligned relatively deep trench in accordance with the present invention is formed over the gate regions. This is achieved by forming an oxide layer, and forming a polysilicon layer on the oxide layer. A second oxide layer is formed on the polysilicon layer which is then masked by a self-aligning mask. Trenches are etched into the source and gate regions using the self-aligning mask and gate regions are formed at the bottom of the trenches. The transistors are then processed to completion by forming gate, source and drain regions.

Abstract: Submicron channel length FET is fabricated using larger (e.g., 1 micron) design rule fabrication equipment. A polysilicon layer (34) is first formed over an active device region (28). The following transistor elements are then sequentially formed using a single mask opening (38): [1] threshold adjust implant (40) by implanting impurity ions into the active device region surface; [2] LDD implant regions (42) by implanting impurity ions into lower portion of the polysilicon layer (38); and [3] source/drain doped implant regions (44) by implanting impurity ions into the upper portion of polysilicon layer (38). A gate opening (60) is next formed in the polysilicon layer (38) and overlying dielectric layer (57) using large design rule lithography to pattern, and then by etching. Sidewall spacers (66) are formed at a submicron distance apart in the gate opening (60), defining gate length (68) therebetween.

Abstract: A method for fabricating a super self-aligned bipolar junction transistor which reduces or eliminates emitter defects caused during critical etching steps by providing a non-critically thick dielectric etch stop (protection) layer (116) during all potentially damaging etching steps. An oxide or other dielectric layer (116, 130), is provided above the emitter region (152) of the semiconductor surface (110) during potentially damaging etching steps, such as dry etch procedures used to form critical device structures such as emitter opening 124 and sidewall spacers 146. Non-damaging etching procedures, such as wet etching, are used to remove dielectric protection layers (116, 130) to form less critical device structures, and/or form intermediate layer openings without damaging the silicon surface in the emitter (152), or other critical regions.

Abstract: A method of forming a contact diffusion barrier in a thin geometry integrated circuit device involves implanting a second material into a low resistivity material that overlies the semiconductor to which contact is desired. The low resistivity and implanted materials are selected to intereact with each other and form a contact diffusion barrier. Both materials may include transition metals, in which case the diffusion barrier is a composite transition metal. Alternately, the low resistivity material may include a transition metal, while implantation is performed with nitrogen. The implantation is performed by plasma etching, preferably with active cooling, which can be combined in a continuous step with the etching of the contact opening. The resulting contact diffusion barrier is self-aligned with the contact opening, and is established only in the immediate vicinity of the opening.

Abstract: A modification of the self-aligned double poly fabrication process for bipolar transistors employs a thin sacrificial dielectric film to protect the wafer surface during the etching of an emitter opening through an overlying polysilicon contact layer. The sacrificial layer, which is preferably silicon dioxide for a silicon wafer, is thick enough to serve as an etch stop but thin enough to permit dopant from the polysilicon contact to be driven-in through the film to form an extrinsic base region. The dielectric film is left in place under the base contact polysilicon, but removed from the emitter area. It is preferably about 10-20 Angstroms thick when implemented as a silicon dioxide film. With this material system, the extrinsic base drive-in is preferably performed either by a rapid isothermal anneal at about 1,000.degree. C. for about 30-40 seconds, or in a furnace at about 975.degree. C. for about 10 minutes.

Abstract: A complementary bipolar CMOS fabrication method uses a common deposition for both the CMOS gate contacts, and as a sacrificial layer for patterning bipolar devices. The deposition is removed from the bipolar devices and, after implanting base and emitter regions, is replaced with a separate emitter contact. Prior to its removal the sacrificial layer is coated with an oxidation resistant layer that imparts a desirable rounded shape to the edge of a thermal oxide layer that is grown around the bipolar emitter area. Common mask and implant steps are also used to fabricate lightly doped CMOS drains together with bipolar base-link regions, and CMOS source/drain regions together with bipolar external base regions. The fabrication technique also facilitates the fabrication of capacitors with no additional steps required, and includes an improved NiCr resistor contact method.

Abstract: A method of forming a contact diffusion barrier in a thin geometry integrated circuit device involves implanting a second material into a low resistivity material that overlies the semiconductor to which contact is desired. The low resistivity and implanted materials are selected to intereact with each other and form a contact diffusion barrier. Both materials may include transition metals, in which case the diffusion barrier is a composite transition metal. Alternately, the low resistivity material may include a transition metal, while implantation is performed with nitrogen. The implantation is performed by plasma etching, preferably with active cooling, which can be combined in a continuous step with the etching of the contact opening. The resulting contact diffusion barrier is self-aligned with the contact opening, and is established only in the immediate vicinity of the opening.

Abstract: A method of fabricating self aligned static induction transistors. The method comprises fabricating an N silicon on N.sup.- silicon substrate having an active area. A guard ring is formed around the active area. An N.sup.+ polysilicon layer is formed that comprises source and gate regions. An oxide layer is formed on the N.sup.+ polysilicon layer. A second polysilicon layer is formed on the oxide layer. A second oxide layer is formed on the second polysilicon layer which is then masked by a self aligning mask. Trenches are etched into the substrate using the self aligning mask and gate regions are formed at the bottom of the trenches. A first layer of metal (gate metal) is deposited to make contact with the gate regions. A layer of photoresist is deposited and planarized, and the first layer of metal is overetched below the top surface of the trench. Plasma nitride is deposited and planarized, and a polysilicon mask is deposited over the planarized layer of plasma nitride.

Abstract: Complimentary metal oxide silicon transistors fabricated on silicon-on-insulator substrates are configured to allow separately controllable and independent backgate bias for adjacent complimentary devices on the same substrate. By means of deep implantation of boron, a backgate bias P- well (26,126) is positioned on the N-substrate (17,117) at a front surface of the N- substrate behind the N channel transistor of a complimentary pair. The backgate bias P- well (26,126) is provided with an electrical contact (48,148) at the front of the device, as is the N- silicon substrate to enable independent application of separate bias voltage of different polarities and appropriate magnitude.

Abstract: High speed silicon-on-insulator radiation hardened semiconductor devices and a method of fabricating same. Starting with a SIMOX wafer (10) having a layer of silicon (12) on a layer of buried oxide (11), P-well and N-well masks are aligned to an oversized polysilicon mask (16). This produces relatively thick source and drain regions (18) and relatively thin gate regions (17). The relatively thick source and drain regions (18) educe the risk of dry contact etch problems. N-channel and P-channel threshold voltages are adjusted prior to the formation of active areas, thus substantially eliminating edge and back channel leakage. A sacrificial thin oxide layer (21) is employed in fabricating the N-well and P-well implants so that both front and back channel threshold voltage adjustments are controlled. Good control of doping profiles is obtained, leading to excellent threshold voltage control and low edge and back channel leakages.

Abstract: High speed silicon-on-insulator radiation hardened semiconductor devices and a method of fabricating same. Starting with a SIMOX wafer (10) having a layer of silicon (12) on a layer of buried oxide (11), P-well and N-well masks are aligned to an oversized polysilicon mask (16). This produces relatively thick source and drain regions (18) and relatively thin gate regions (17). The relatively thick source and drain regions (18) reduce the risk of dry contact etch problems. N-channel and P-channel threshold voltages are adjusted prior to the formation of active areas, thus substantially eliminating edge and back cannel leakage. A sacrificial thin oxide layer (21) is employed in fabricating the N-well and P-well implants so that both front and back channel threshold voltage adjustments are controlled. Good control of doping profiles is obtained, leading to excellent threshold voltage control and low edge and back channel leakages.

Abstract: A method of fabricating higher-order metal interconnection layers in a multi-level metal semiconductor device. The semiconductor device has at least one metal layer, an oxide layer disposed on the metal layer, and a metal plug disposed in the oxide layer connected to the metal layer. A reverse photoresist mask is formed on the oxide layer that is etched to form trenches therein that define the higher-order metal layer. An adhesion layer that comprises titanium tungsten or aluminum is deposited on top of the photoresist mask that contacts the metal plug. A low viscosity photoresist layer is then deposited on top of the adhesion layer. The adhesion layer and low viscosity photoresist layer are then anisotropically etched, and the low viscosity photoresist layer is then removed to expose the adhesion layer. Finally, selective metal, such as tungsten or molybdenum, for example, is deposited on top of the adhesion layer in the trench to form the higher-order metal interconnection layer.

Abstract: Methods of fabricating metal interconnection lines in an integrated circuit. In general, one method comprises the steps of depositing a layer of metal on an inter-dielectric oxide layer. The layer of metal is patterned and etched to form metal interconnection lines over the oxide layer. Tungsten is selectively deposited onto the etched layer to completely form the metal interconnection lines. Additionally, in a second method, a layer of tungsten may be deposited prior to the layer of metal. This forms a metal line that is completely encapsulated in tungsten. In addition, selective tungsten employed to repair broken metal lines in a fabricated integrated circuit. The selective tungsten is deposited using a chemical vapor deposition process and is deposited onto masked and etched second level (or higher) metal lines formed in the integrated circuit. The method of selectively depositing tungsten comprises the steps of exposing the metal interconnection lines to a mixture of SiH.sub.

Abstract: A process for forming a diffusion barrier on exposed silicon and polysilicon contacts of an integrated circuit including the step of chemically vapor depositing a layer of tungsten in a self-aligned manner on the exposed contact areas. The layer of tungsten is plasma nitridated to form a tungsten nitride layer and to partially form a tungsten silicide layer adjacent the contact areas. The formation of the tungsten silicide layer is completed by thermal annealing.