Patents by Inventor Max Liu

Max Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240021727
    Abstract: The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.
    Type: Application
    Filed: July 20, 2023
    Publication date: January 18, 2024
    Inventors: Max Liu, Yen-Ming Peng, Wei-Shuo Ho
  • Patent number: 11804547
    Abstract: The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: October 31, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Max Liu, Yen-Ming Peng, Wei-Shuo Ho
  • Publication number: 20220322790
    Abstract: An article of footwear includes an upper and a sole structure attached to the upper. The article of footwear also includes a cable lock disposed within the sole structure adjacent to a bottom surface of the sole structure. The article of footwear includes a first cable having a first section extending from the cable lock to a first anchor point on the upper and a second section extending from the cable lock to a second anchor point on the upper. The article of footwear further includes a second cable having a first section extending from the cable lock to a grip and a second section extending from the cable lock to the grip, whereby the cable lock is operable to retract the first section and the second section of the first cable when the first section and the second section of the second cable are extended.
    Type: Application
    Filed: June 28, 2022
    Publication date: October 13, 2022
    Applicant: NIKE, Inc.
    Inventors: George Chiou, Ross Klein, Tate E. Kuerbis, Max Liu, Austin J. Orand, Nuryani K. Sulistyo, Harry Y. Sun
  • Patent number: 11382390
    Abstract: An article of footwear includes an upper and a sole structure attached to the upper. The article of footwear also includes a cable lock disposed within the sole structure adjacent to a bottom surface of the sole structure. The article of footwear includes a first cable having a first section extending from the cable lock to a first anchor point on the upper and a second section extending from the cable lock to a second anchor point on the upper. The article of footwear further includes a second cable having a first section extending from the cable lock to a grip and a second section extending from the cable lock to the grip, whereby the cable lock is operable to retract the first section and the second section of the first cable when the first section and the second section of the second cable are extended.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: July 12, 2022
    Assignee: NIKE, Inc.
    Inventors: George Chiou, Ross Klein, Tate E. Kuerbis, Max Liu, Austin J. Orand, Nuryani K. Sulistyo, Harry Y. Sun
  • Publication number: 20210384350
    Abstract: The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.
    Type: Application
    Filed: August 24, 2021
    Publication date: December 9, 2021
    Inventors: Max Liu, Yen-Ming Peng, Wei-Shuo Ho
  • Patent number: 11107922
    Abstract: The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.
    Type: Grant
    Filed: December 29, 2019
    Date of Patent: August 31, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Max Liu, Yen-Ming Peng, Wei-Shuo Ho
  • Patent number: 11060640
    Abstract: A pipe connector has a tube and two binding rings. The tube is made from a soft material and forms at least one fixing segment on two ends. The two binding rings are mounted on the two ends of the tube respectively. Each binding ring has at least one locating segment. The amount of the at least one locating segment is equal to the amount of the at least one fixing segment of the tube. The at least one fixing segment engages with the at least one locating segment to fix the binding ring and the tube. Thus, a user only needs to expand the tube to mount the tube onto a water pipe instead of heating it. Alternatively, engaging the fixing segment with the locating segment prevents the binding ring from moving relatively to the tube.
    Type: Grant
    Filed: March 7, 2019
    Date of Patent: July 13, 2021
    Assignee: ALL GAIN INDUSTRY CO., LTD.
    Inventor: Max Liu
  • Patent number: 10840376
    Abstract: The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.
    Type: Grant
    Filed: January 31, 2018
    Date of Patent: November 17, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Max Liu, Yen-Ming Peng, Wei-Shuo Ho
  • Publication number: 20200248849
    Abstract: A pipe connector has a tube and two binding rings. The tube is made from a soft material and forms at least one fixing segment on two ends. The two binding rings are mounted on the two ends of the tube respectively. Each binding ring has at least one locating segment. The amount of the at least one locating segment is equal to the amount of the at least one fixing segment of the tube. The at least one fixing segment engages with the at least one locating segment to fix the binding ring and the tube. Thus, a user only needs to expand the tube to mount the tube onto a water pipe instead of heating it. Alternatively, engaging the fixing segment with the locating segment prevents the binding ring from moving relatively to the tube.
    Type: Application
    Filed: March 7, 2019
    Publication date: August 6, 2020
    Applicant: ALL GAIN INDUSTRY CO., LTD.
    Inventor: Max LIU
  • Publication number: 20200144422
    Abstract: The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.
    Type: Application
    Filed: December 29, 2019
    Publication date: May 7, 2020
    Inventors: Max Liu, Yen-Ming Peng, Wei-Shuo Ho
  • Publication number: 20200085144
    Abstract: An article of footwear includes an upper and a sole structure attached to the upper. The article of footwear also includes a cable lock disposed within the sole structure adjacent to a bottom surface of the sole structure. The article of footwear includes a first cable having a first section extending from the cable lock to a first anchor point on the upper and a second section extending from the cable lock to a second anchor point on the upper. The article of footwear further includes a second cable having a first section extending from the cable lock to a grip and a second section extending from the cable lock to the grip, whereby the cable lock is operable to retract the first section and the second section of the first cable when the first section and the second section of the second cable are extended.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 19, 2020
    Applicant: NIKE, Inc.
    Inventors: George Chiou, Ross Klein, Tate E. Kuerbis, Max Liu, Austin J. Orand, Nuryani K. Sulistyo, Harry Y. Sun
  • Publication number: 20190308531
    Abstract: A safety seat (100) includes a seat body (10) and a set of caster wheels (11). The safety seat can ride on the caster wheels (11). The safety seat can also include a handle (12) for easy manipulation and a footrest (13) for the child to rest the feet. The caster wheels (11), the handle (12) and the footrest (13) can be retracted when they are not used and extended out when needed.
    Type: Application
    Filed: April 4, 2018
    Publication date: October 10, 2019
    Inventors: Max Liu, Xin Jiang
  • Publication number: 20190165173
    Abstract: The semiconductor structure includes a semiconductor substrate having a first region and a second region being adjacent to the first region; first fins formed on the semiconductor substrate within the first region; a first shallow trench isolation (STI) feature disposed on the semiconductor substrate within the second region; and a first gate stack that includes a first segment disposed directly on the first fins within the first region and a second segment extending to the first STI feature within the second region. The second segment of the first gate stack includes a low resistance metal (LRM) layer, a first tantalum titanium nitride layer, a titanium aluminum nitride layer, and a second tantalum titanium nitride layer stacked in sequence. The first segment of the first gate stack within the first region is free of the LRM layer.
    Type: Application
    Filed: January 31, 2018
    Publication date: May 30, 2019
    Inventors: Max Liu, Yen-Ming Peng, Wei-Shuo Ho
  • Patent number: 8704375
    Abstract: Through substrate via barrier structures and methods are disclosed. In one embodiment, a semiconductor device includes a first substrate including an active device region disposed within isolation regions. A through substrate via is disposed adjacent to the active device region and within the first substrate. A buffer layer is disposed around at least a portion of the through substrate via, wherein the buffer layer is disposed between the isolation regions and the through substrate via.
    Type: Grant
    Filed: November 5, 2009
    Date of Patent: April 22, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Max Liu, Chao-Shun Hsu, Ya-Wen Tseng, Wen-Chih Chiou, Weng-Jin Wu
  • Publication number: 20100193954
    Abstract: Through substrate via barrier structures and methods are disclosed. In one embodiment, a semiconductor device includes a first substrate including an active device region disposed within isolation regions. A through substrate via is disposed adjacent to the active device region and within the first substrate. A buffer layer is disposed around at least a portion of the through substrate via, wherein the buffer layer is disposed between the isolation regions and the through substrate via.
    Type: Application
    Filed: November 5, 2009
    Publication date: August 5, 2010
    Inventors: Max Liu, Chao-Shun Hsu, Ya-Wen Tseng, Wen-Chih Chiou, Weng-Jin Wu