Abstract: An RF amplifier suitable for use in an RF transceiver has a circuit including a first transistor pair with the collector of each coupled to one of the two differential output nodes and a common base. A pair of Ft doublers is provided with the emitter of each Ft doubler coupled to one of the transistors in the first transistor pair. Each Ft doubler has a common emitter and a base coupled to one of the differential input nodes. As such, the first transistor pair and the Ft doubler pair are cascode-coupled to provide a wide bandwidth, high gain, and high input impedance RF amplifier.

Abstract: A programmable divider or prescaler divides an input signal by a divisor of two raised to the m.sup.th -power plus one, (2.sup.m +1), where m is an integer, and n is a value between zero and two raised to the m.sup.th -power minus one, (2.sup.m -1). When m is equal to 3, the duty cycle is between 44% and 56%. The divider can be utilized in communication applications for providing radio frequency source signals. The duty cycle is maintained around 50% for use with balanced mixers.