Abstract: A computer/software tool for electronic design automation (EDA) extracts parasitics from a post-layout netlist file for an integrated circuit (IC) design and uses these parasitics to model circuit behavior between one or more excitation points and one or more observation points for a given circuit design characteristic. Sensitivities of that given circuit design characteristic to each constituent parasitic (or a group of parasitics that might be, for example, associated with a given structural element such as a layer) are then computed. The computer/software tool generates a visual display based on the relative sensitivities; for example, in one embodiment, relative sensitivities can be color-coded to permit a designer to visualize sources of problems in the IC design. In other embodiments, the sensitivities can be filtered and/or processed, e.g., so as to provide EDA driven assistance to changes to reduce excessive sensitivities or sensitivities to certain parasitics.

Abstract: A computer/software tool for electronic design automation (EDA) uses parasitic elements from a post-layout netlist (PLN) file for a given IC design to assess routing-imposed RC-based signal degeneration. The computer/software tool facilitates selection of, and insertion location for, one or more “virtual repeaters,” based on modification to the PLN file. The tool generates a visual display based on the calculated design characteristics, facilitating adjustment and optimization of repeater cell and location by the designer. The repeater insertion is “virtual,” because modeling and adjustment can be based on abstractions (e.g., load capacitance presented by a repeater) and the already-extracted netlist file, and because an actual circuit design need not be created until after a designer has fine-tuned repeater insertion parameters.

Abstract: A computer/software tool for electronic design automation (EDA) extracts parasitics from a post-layout netlist file for an integrated circuit (IC) design and uses these parasitics to model circuit behavior specifically to assess matching of reciprocal objects of a matched circuit. The computer/software tool generates a visual display based on the calculated design characteristics; for example, in one embodiment, asymmetry can be color-coded to permit a designer to visualize sources of matching problems base on mismatched parasitics. In other embodiments, the parasitics, structural elements and/or results can be filtered and/or processed, e.g., so as to provide EDA driven assistance to reduce excessive sensitivity to certain parasitics, and to minimize net and device systematic (layout-based) mismatch.

Abstract: A computer/software tool for electronic design automation (EDA) extracts parasitics from a post-layout netlist file for an integrated circuit (IC) design and uses these parasitics to model circuit behavior specifically to assess matching of reciprocal objects of a matched circuit. The computer/software tool generates a visual display based on the calculated design characteristics; for example, in one embodiment, asymmetry can be color-coded to permit a designer to visualize sources of matching problems base on mismatched parasitics. In other embodiments, the parasitics, structural elements and/or results can be filtered and/or processed, e.g., so as to provide EDA driven assistance to reduce excessive sensitivity to certain parasitics, and to minimize net and device systematic (layout-based) mismatch.

Abstract: A computer/software tool for electronic design automation (EDA) uses parasitic elements from a post-layout netlist (PLN) file for a given IC design to assess routing-imposed RC-based signal degeneration. The computer/software tool facilitates selection of, and insertion location for, one or more “virtual repeaters,” based on modification to the PLN file. The tool generates a visual display based on the calculated design characteristics, facilitating adjustment and optimization of repeater cell and location by the designer. The repeater insertion is “virtual,” because modeling and adjustment can be based on abstractions (e.g., load capacitance presented by a repeater) and the already-extracted netlist file, and because an actual circuit design need not be created until after a designer has fine-tuned repeater insertion parameters.

Abstract: A computer/software tool for electronic design automation (EDA) extracts parasitics from a post-layout netlist file for an integrated circuit (IC) design and uses these parasitics to model circuit behavior specifically to assess matching of reciprocal objects of a matched circuit. The computer/software tool generates a visual display based on the calculated design characteristics; for example, in one embodiment, asymmetry can be color-coded to permit a designer to visualize sources of matching problems base on mismatched parasitics. In other embodiments, the parasitics, structural elements and/or results can be filtered and/or processed, e.g., so as to provide EDA driven assistance to reduce excessive sensitivity to certain parasitics, and to minimize net and device systematic (layout-based) mismatch.

Abstract: A computer/software tool for electronic design automation (EDA) extracts parasitics from a post-layout netlist file for an integrated circuit (IC) design and uses these parasitics to model circuit behavior between one or more excitation points and one or more observation points for a given circuit design characteristic. Sensitivities of that given circuit design characteristic to each constituent parasitic (or a group of parasitics that might be, for example, associated with a given structural element such as a layer) are then computed. The computer/software tool generates a visual display based on the relative sensitivities; for example, in one embodiment, relative sensitivities can be color-coded to permit a designer to visualize sources of problems in the IC design. In other embodiments, the sensitivities can be filtered and/or processed, e.g., so as to provide EDA driven assistance to changes to reduce excessive sensitivities or sensitivities to certain parasitics.

Abstract: Method and apparatus for an integrated circuit having memory including thyristor-based memory cells is described. A pair of the thyristor-based memory cells are commonly coupled via a bitline region, where a parasitic bipolar junction transistor is defined therebetween responsive to the bitline region being common. In another implementation, the pair of the thyristor-based memory cells are commonly coupled via the anode region, where a parasitic bipolar junction transistor is defined therebetween responsive to the anode region being common. The common bitline or anode region, respectively, has a locally thinned region to inhibit charge transfer between the pair via the parasitic bipolar junction transistor. Moreover, a method for forming a field-effect transistor on a silicon-on-insulator wafer is described, where charge transfer facilitated by a parasitic bipolar transistor is reduced responsive to an increase in dopants at least proximate to an insulator layer.

Abstract: A method for forming a photodiode cathode in an integrated circuit imager includes defining and implanting a photodiode cathode region with a photodiode cathode implant dose of a dopant species and defining and implanting an edge region of the photodiode cathode region with a photodiode cathode edge implant dose of a dopant species to form a region of higher impurity concentration than the photodiode cathode impurity concentration.

Abstract: In accordance with an embodiment of the present invention, a semiconductor memory device includes an array of thyristor-based memory formed in a silicon-on-insulator (SOI) supporting substrate. A portion of the supporting structure of the SOI substrate has a density of dopants sufficient to assist delivery of a bias to the backside of an insulating layer beneath a thyristor of the thyristor-based semiconductor memory. By enabling biasing of the substrate at the backside of the insulating layer beneath the thyristor, a back-gate control is available for controlling or compensating the gain of a component bipolar device of the thyristor with respect to temperature.

Abstract: In accordance with an embodiment of the present invention, a thyristor-based semiconductor memory device may comprise an array of thyristor-based memory formed in an SOI wafer. A supporting substrate may be formed with a density of dopants sufficient to assist delivery of a bias level to the backside of an insulating layer beneath a thyristor. Such conductivity within the substrate may allow reliable back-gate control for the gain of a component bipolar device of the thyristor.