Patents by Inventor Maxim Klebanov
Maxim Klebanov has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20190363162Abstract: A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.Type: ApplicationFiled: August 12, 2019Publication date: November 28, 2019Applicant: Allegro MicroSystems, LLCInventors: Sundar Chetlur, Maxim Klebanov, Washington Lamar
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Patent number: 10468485Abstract: A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.Type: GrantFiled: May 26, 2017Date of Patent: November 5, 2019Assignee: Allegro MicroSystems, LLCInventors: Sundar Chetlur, Maxim Klebanov, Washington Lamar
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Publication number: 20190265018Abstract: Methods and apparatus for a sensor with a main coil to direct a magnetic field at a rotating target for inducing eddy currents in an end of the target and a sensing element to detect a magnetic field reflected from the target, wherein the target end comprises a conductive surface. The reflected magnetic field can be processed to determine an angular position of the target.Type: ApplicationFiled: February 22, 2019Publication date: August 29, 2019Applicant: Allegro MicroSystems, LLCInventors: Alexander Latham, Maxim Klebanov
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Publication number: 20190155322Abstract: An electronic circuit includes a driver circuit having an output terminal that can be coupled to a load to drive the load. A control circuit is coupled to the driver circuit for controlling the driver circuit. A transistor is coupled in series between the driver circuit and the output terminal. The transistor has a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal. A biasing circuit is coupled to a gate terminal of the transistor and configured to provide a constant voltage to the gate terminal to bias the transistor to a conducting state to reduce the susceptibility of the electronic circuit to electromagnetic interference. The biasing circuit includes a voltage regulator, a Zener diode, and a capacitor. The Zener diode and capacitor are coupled to the gate terminal and a reference terminal.Type: ApplicationFiled: January 28, 2019Publication date: May 23, 2019Applicant: Allegro MicroSystems, LLCInventors: Richard B. Cooper, Maxim Klebanov, Washington Lamar, Devon Fernandez
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Patent number: 10256225Abstract: A gate-less electrostatic discharge (ESD) protection device is provided that can be formed in various complementary metal-oxide-semiconductor (CMOS) systems. The gate-less ESD event protection device includes a substrate, a first doped region formed in the substrate, a second doped region extending into the first doped region, a third doped region extending into the first doped region, a first node formed over a portion of the second doped region and coupled to a source terminal and a second node formed over the third doped region and coupled to a drain terminal. The gate-less ESD protection devices can be formed such that no gate electrode is formed and the gate-less ESD protection device does not include a gate terminal. Thus, an operating voltage range of the gate-less ESD protection device is not limited by gate oxide degradation.Type: GrantFiled: May 22, 2017Date of Patent: April 9, 2019Assignee: Allegro MicroSystems, LLCInventors: Maxim Klebanov, Washington Lamar
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Patent number: 10234887Abstract: An electronic circuit includes semiconductor substrate having a first doping type and a reference terminal coupled to the semiconductor substrate. A tub area having a second doping type is formed in the semiconductor substrate. A well area having the first doping type is formed within the tub area. A driver circuit comprising a transistor is formed within the well area and has an output terminal. A control circuit is coupled to the driver circuit for controlling the driver circuit. A second transistor is within the well area and coupled in series between the driver circuit and the output terminal, the second transistor having a first terminal coupled to the driver circuit and a second terminal coupled to the output terminal. A biasing circuit is coupled to a gate terminal of the second transistor and configured to bias the transistor to a conducting state.Type: GrantFiled: May 23, 2016Date of Patent: March 19, 2019Assignee: Allegro MicroSystems, LLCInventors: Richard B. Cooper, Maxim Klebanov, Washington Lamar, Devon Fernandez
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Publication number: 20190067562Abstract: Methods and apparatus for a signal isolator having a dielectric interposer supporting first and second die each having a magnetic field sensing element. A first signal path extends from the first die to the second die and a second signal path extends from the second die to the first die. In embodiments, the first signal path is located in the interposer and includes a first coil to generate a magnetic field and the second signal path is located in the interposer and includes a second coil to generate a magnetic filed. The first coil is located in relation to the second magnetic field sensing element of the second die and the second coil is located in relation to the first magnetic field sensing element of the first die.Type: ApplicationFiled: August 29, 2017Publication date: February 28, 2019Applicant: Allegro MicroSystems, LLCInventors: Sundar Chetlur, Harianto Wong, Maxim Klebanov, William P. Taylor, Michael C. Doogue
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Patent number: 10147688Abstract: An integrated circuit device includes a package and at least two leads exposed external to the package to permit electrical connections to the package. A first die situated in the package has a first substrate and at least a first terminal electrically coupled to a first one of the leads. A second die situated in the package has a second substrate and at least a second terminal electrically coupled to a second one of the lead. An adhesive material holding the first and second die in place forms a voltage-triggered conduction path between the first and second die electrically that isolates the second die from the first die under a first condition and provides an ESD current path between the first one of the leads and the second one of the leads under a second condition.Type: GrantFiled: February 25, 2016Date of Patent: December 4, 2018Assignee: Allegro Microsystems, LLCInventors: William Wilkinson, Washington Lamar, Maxim Klebanov
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Patent number: 10147689Abstract: An electronic device includes a package, a plurality of external leads extending outside the package, a first die within the package having one or more first contacts electrically coupled to at least a first one of the external leads, and a second die within the package having one or more second contacts electrically coupled to at least a second one of the external leads. A capacitive coupling may be positioned between the first and second die to allow electrostatic discharge (ESD) current to flow between the first die and the second die in response to an ESD event and to electrically isolate the first and second die from each other in the absence of the ESD event.Type: GrantFiled: February 28, 2018Date of Patent: December 4, 2018Assignee: Allegro MicroSystems, LLCInventors: Washington Lamar, Maxim Klebanov
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Patent number: 10145904Abstract: An apparatus includes a package, a plurality of external connections extending outside the package, and a first die having a first electrical contact coupled to a first connection of the plurality of external connections. The apparatus also includes a second die having a second electrical contact coupled to a second connection of the plurality of external connections. A conductor is electrically coupled between the first contact and the second contact to allow electrostatic discharge current to flow between the first die to the second die.Type: GrantFiled: August 24, 2016Date of Patent: December 4, 2018Assignee: Allegro MicroSystems, LLCInventors: Maxim Klebanov, Washington Lamar, William P. Taylor
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Publication number: 20180342500Abstract: A metal-oxide semiconductor (MOS) transistor structure is provided herein having one or more horizontal and/or one or more vertical MOS transistor structures formed around trench and liner isolation regions. The trench region serves as a gate electrode, while the liner is formed around the sidewalls of trench region and serves as a gate dielectric of a parasitic MOS within the transistor structure. The MOS transistor structure includes various doped regions formed around one or more portions of the trench and liner regions. The doped regions can have one or more different doping types such that in response to a voltage applied to the trench region, a channel region is formed in at least one of the doped regions and provides a current path within the MOS transistor between different doped regions.Type: ApplicationFiled: May 26, 2017Publication date: November 29, 2018Applicant: Allegro Microsystems, LLCInventors: Sundar Chetlur, Maxim Klebanov, Washington Lamar
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Publication number: 20180337168Abstract: A gate-less electrostatic discharge (ESD) protection device is provided that can be formed in various complementary metal-oxide-semiconductor (CMOS) systems. The gate-less ESD event protection device includes a substrate, a first doped region formed in the substrate, a second doped region extending into the first doped region, a third doped region extending into the first doped region, a first node formed over a portion of the second doped region and coupled to a source terminal and a second node formed over the third doped region and coupled to a drain terminal. The gate-less ESD protection devices can be formed such that no gate electrode is formed and the gate-less ESD protection device does not include a gate terminal. Thus, an operating voltage range of the gate-less ESD protection device is not limited by gate oxide degradation.Type: ApplicationFiled: May 22, 2017Publication date: November 22, 2018Applicant: Allegro Microsystems, LLCInventors: Maxim Klebanov, Washington Lamar
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Patent number: 10056364Abstract: An electrical device may include a substrate; a first doped region of the substrate having a p doping type; a second doped region adjacent to the first doped region of the substrate having an n doping type, wherein an interface between the first and second doped regions forms a p-n junction; and a circuit element placed in spaced relation to the p-n junction, the circuit element configured to produce an electric field that interacts with the p-n junction to change a reverse breakdown voltage of the p-n junction. Applicants for the electrical device include ESD protection circuits.Type: GrantFiled: April 7, 2017Date of Patent: August 21, 2018Assignee: Allegro MicroSystems, LLCInventors: Maxim Klebanov, Washington Lamar, Richard B. Cooper, Chung C. Kuo
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Patent number: 10050193Abstract: In one aspect, a magnetoresistance structure includes a magnetoresistance stack that includes a plurality of layers that includes a first set of one or more magnetoresistance layers and a second set of one or more magnetoresistance layers. The magnetoresistance structure also includes side walls attached to the sides of the first set of one or more magnetoresistance layers and disposed on the second set of one or more magnetoresistance layers.Type: GrantFiled: June 5, 2017Date of Patent: August 14, 2018Assignee: Allegro MicroSystems, LLCInventors: Maxim Klebanov, Paolo Campiglio, Yu-Ming Wang
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Publication number: 20180190599Abstract: An electronic device includes a package, a plurality of external leads extending outside the package, a first die within the package having one or more first contacts electrically coupled to at least a first one of the external leads, and a second die within the package having one or more second contacts electrically coupled to at least a second one of the external leads. A capacitive coupling may be positioned between the first and second die to allow electrostatic discharge (ESD) current to flow between the first die and the second die in response to an ESD event and to electrically isolate the first and second die from each other in the absence of the ESD event.Type: ApplicationFiled: February 28, 2018Publication date: July 5, 2018Applicant: Allegro MicroSystems, LLCInventors: Washington Lamar, Maxim Klebanov
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Patent number: 9941224Abstract: An electronic device includes a package, a plurality of external leads extending outside the package, a first die within the package having one or more first contacts electrically coupled to at least a first one of the external leads, and a second die within the package having one or more second contacts electrically coupled to at least a second one of the external leads. A capacitive coupling may be positioned between the first and second die to allow electrostatic discharge (ESD) current to flow between the first die and the second die in response to an ESD event and to electrically isolate the first and second die from each other in the absence of the ESD event.Type: GrantFiled: August 24, 2016Date of Patent: April 10, 2018Assignee: Allegro MicroSystems, LLCInventors: Washington Lamar, Maxim Klebanov
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Patent number: 9929141Abstract: In one aspect, a silicon-controlled rectifier (SCR) includes a Zener diode embedded in the SCR. In another aspect, a laterally diffused metal oxide semiconductor (LDMOS) includes a Zener diode embedded in the LDMOS. In a further aspect, a lateral insulated-gate bipolar transistor (IGBT) includes a Zener diode embedded in the IGBT.Type: GrantFiled: April 4, 2016Date of Patent: March 27, 2018Assignee: Allegro MicroSystems, LLCInventors: Chung C. Kuo, Maxim Klebanov
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Publication number: 20180083442Abstract: An apparatus includes a first terminal, a second terminal, and a conduction path circuit coupled between the first and second terminals. The conduction path circuit includes an input terminal to receive an enable signal which, when activated, allows the conduction path circuit to conduct electrical current between the first and second terminal. A control circuit coupled to the input terminal of the conduction path circuit is configured to selectively activate the enable signal.Type: ApplicationFiled: September 22, 2016Publication date: March 22, 2018Applicant: Allegro MicroSystems, LLCInventors: Washington Lamar, Maxim Klebanov
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Patent number: 9910087Abstract: An integrated circuit includes at least one first magnetic field sensing element including at least one first magnetoresistance element configured to provide an output signal of the integrated circuit in response to a detected magnetic field. The integrated circuit also includes at least one second magnetic field sensing element including at least one second magnetoresistance element configured to have a characteristic indicative of a stress condition. A method for detecting a stress condition in an integrated circuit is also provided.Type: GrantFiled: March 14, 2016Date of Patent: March 6, 2018Assignee: Allegro Microsystems, LLCInventors: Jeffrey Eagen, Maxim Klebanov, William P. Taylor
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Publication number: 20180061784Abstract: An electronic device includes a package, a plurality of external leads extending outside the package, a first die within the package having one or more first contacts electrically coupled to at least a first one of the external leads, and a second die within the package having one or more second contacts electrically coupled to at least a second one of the external leads. A capacitive coupling may be positioned between the first and second die to allow electrostatic discharge (ESD) current to flow between the first die and the second die in response to an ESD event and to electrically isolate the first and second die from each other in the absence of the ESD event.Type: ApplicationFiled: August 24, 2016Publication date: March 1, 2018Applicant: Allegro MicroSystems, LLCInventors: Washington Lamar, Maxim Klebanov