Abstract: An image sensor architecture with multi-bit sampling is implemented within an image sensor system. A pixel signal produced in response to light incident upon a photosensitive element is converted to a multiple-bit digital value representative of the pixel signal. If the pixel signal exceeds a sampling threshold, the photosensitive element is reset. During an image capture period, digital values associated with pixel signals that exceed a sampling threshold are accumulated into image data.

Abstract: Methods and systems for increasing the effective dynamic range of an image sensor are disclosed. Each pixel in the sensor is exposed for a respective first exposure time. Each pixel's response to the respective first exposure is measured and compared to threshold values. Based on the pixel's response to the respective first exposure time, an optimal exposure is calculated for each pixel. The optimal exposure time is applied to each pixel by utilizing row-enabled and column-enabled signals at each pixel within the sensor.

Abstract: An image sensor architecture with multi-bit sampling is implemented within an image sensor system. A pixel signal produced in response to light incident upon a photosensitive element is converted to a multiple-bit digital value representative of the pixel signal. If the pixel signal exceeds a sampling threshold, the photosensitive element is reset. During an image capture period, digital values associated with pixel signals that exceed a sampling threshold are accumulated into image data.

Abstract: An image processor comprises first and second hardware accelerators and is configured to implement a classifier. The classifier in some embodiments comprises a cascaded classifier having a plurality of stages with each such stage implementing a plurality of decision trees. At least one of the first and second hardware accelerators of the image processor is configured to generate an integral image based on a given input image, and the second hardware accelerator is configured to process image patches of the integral image through one or more of a plurality of decision trees of the classifier implemented by the image processor. By way of example, the first and second hardware accelerators illustratively comprise respective front-end and back-end accelerators of the image processor, and an integral image calculator configured to generate the integral image based on the given input image is implemented in one of the front-end accelerator and the back-end accelerator.

Abstract: Methods and systems for increasing the effective dynamic range of an image sensor are disclosed. Each pixel in the sensor is exposed for a respective first exposure time. Each pixel's response to the respective first exposure is measured and compared to threshold values. Based on the pixel's response to the respective first exposure time, an optimal exposure is calculated for each pixel. The optimal exposure time is applied to each pixel by utilizing row-enabled and column-enabled signals at each pixel within the sensor.

Abstract: High level synthesis techniques are disclosed, particularly, techniques for synthesizing pipelines having distributed control. In some implementations, an algorithmic description for a device design is first identified. Subsequently, a data-flow representation of the algorithmic description is generated; the data-flow representation including a plurality of operations. The plurality of operations are then scheduled, following which, a plurality of pipeline stages are generated corresponding to ones of the plurality of operations. Control logic for the pipeline stages may then be generated, followed by the generation of a netlist representation of the electronic device design based in part upon the scheduling of operations and pipeline stages.

Abstract: Methods and apparatuses for modeling and simulating a high-level circuit design are provided. With some implementations of the invention, a layered model corresponding to an algorithmic description for a circuit design is generated. The layered model includes a set of threads that describe the behavior of the circuit design, a schedule that describes timing constraints of the circuit design, and interfaces that facilitate the transfer of data between various layered models. With some implementations, a layered model may also include a shared variable that facilitates the transfer of data between ones of the set of threads within a layered model.

Abstract: A target pixel and surrounding pixels corresponding to the target pixel are obtained from a digitally represented image. A bilateral high pass filtering kernel is determined based at least in part upon the target pixel and the surrounding pixels. A high pass spatial filtering kernel is provided and multiplied with the high pass photometric filtering kernel to provide a bilateral high pass filtering kernel. The resulting bilateral high pass filtering kernel is thereafter applied to the target pixel and the surrounding pixels to provide a filtered pixel. When it is desirable to combine noise filtering capabilities with sharpening capabilities, the bilateral high pass filter of the present invention may be combined with a bilateral low pass filtering kernel to provide a combined noise reduction and edge sharpening filter. The present invention may be advantageously applied to a variety of devices, including cellular telephones that employ image sensing technology.

Abstract: The present invention provides a method and apparatus for image processing using a graphics processor in a handheld device including a first memory device receiving a video input signal containing encoded video frame having a plurality of portions of encoded video frame data. The first memory device has a storage capacity less than all of the plurality portions of the encoded video frame data. The method and apparatus further includes the graphics processor coupled to the first memory device, wherein the graphics processor receives the first portion of the encoded video frame data and generates a first graphics portion. A second memory device receives the first graphics portion and stores the first graphics portion therein. As such, the encoded video frame is processed on a portion-by-portion basis using the first memory device and the second memory device in conjunction with the graphics processor.

Abstract: A target pixel and surrounding pixels corresponding to the target pixel are obtained from a digitally represented image. A bilateral high pass filtering kernel is determined based at least in part upon the target pixel and the surrounding pixels. A high pass spatial filtering kernel is provided and multiplied with the high pass photometric filtering kernel to provide a bilateral high pass filtering kernel. The resulting bilateral high pass filtering kernel is thereafter applied to the target pixel and the surrounding pixels to provide a filtered pixel. When it is desirable to combine noise filtering capabilities with sharpening capabilities, the bilateral high pass filter of the present invention may be combined with a bilateral low pass filtering kernel to provide a combined noise reduction and edge sharpening filter. The present invention may be advantageously applied to a variety of devices, including cellular telephones that employ image sensing technology.

Abstract: The present invention provides a method and apparatus for image processing using a graphics processor in a handheld device including a first memory device receiving a video input signal containing encoded video frame having a plurality of portions of encoded video frame data. The first memory device has a storage capacity less than all of the plurality portions of the encoded video frame data. The method and apparatus further includes the graphics processor coupled to the first memory device, wherein the graphics processor receives the first portion of the encoded video frame data and generates a first graphics portion. A second memory device receives the first graphics portion and stores the first graphics portion therein. As such, the encoded video frame is processed on a portion-by-portion basis using the first memory device and the second memory device in conjunction with the graphics processor.

Abstract: For an electromechanical machining of a work piece there is an optimal pulse duration for the machining pulses corresponding to the maximum copying accuracy. Such an optimal pulse duration corresponds to a certain value of the gap. By alternating the machining pulses with measurement pulses it is possible to obtain an accurate information about the gap dimensions on-line during the electrochemical machining process. The process control means (20) are used to automate the electromechanical machining, while keeping it in the optimal mode. For this purpose the process control means (20) comprise the pulse control unit (26) to establish the pulse duration of the voltage pulses to be applied across the gap (4).

Abstract: For an electromechanical machining of a work piece there is an optimal pulse duration for the machining pulses corresponding to the maximum copying accuracy. Such an optimal pulse duration corresponds to a certain value of the gap. By alternating the machining pulses with measurement pulses it is possible to obtain an accurate information about the gap dimensions on-line during the electrochemical machining process. The process control means (20) are used to automate the electromechanical machining, while keeping it in the optimal mode. For this purpose the process control means (20) comprise the pulse control unit (26) to establish the pulse duration of the voltage pulses to be applied across the gap (4).