Abstract: An apparatus to insure safe behavior in an inverter system. In one embodiment, the apparatus includes a first high side gate driver, a first low side gate driver, a microcontroller configured to control the first high side and low side gate drivers. A voltage regulator provides a supply voltage to the microcontroller. A first pair of high side voltage regulators provide a first pair of high side supply voltages to the first high side gate driver. A first pair of low side voltage regulators provide a first pair of low side supply voltages to the first low side gate driver.

Abstract: A semiconductor circuit is disclosed, comprising: a processor; a supply-voltage terminal arranged to receive a supply voltage; an out-of-range-voltage-detection circuit, coupled to the supply-voltage terminal and configured to output a voltage-out-of-range indicator in response to detecting that the supply voltage is out-of-range; a PWM signal generator configured to generate a PWM signal; a power-on-reset request terminal arranged to output the PWM signal during a normal operation of the processor; and logic circuitry between the signal generator and the POR request terminal and configured to modify the PWM signal in response receiving the voltage-out-of-range indicator. A microcontroller circuit incorporating such a semiconductor circuit, and a PMIC circuit for use in conjunction, are also disclosed.

Abstract: Monitoring for an over-voltage condition based on a regulated voltage is disclosed. A first terminal of a voltage regulator receives a first voltage which is based on a regulated voltage input to a controller. A second terminal of the voltage regulator receives a second voltage indicative of the voltage input to the controller. A determination is made whether the first voltage exceeds the first voltage reference for a first time window and the controller is reset based on the determination that the first voltage exceeds the first voltage reference. A determination is also made whether the second voltage exceeds the second voltage reference for the second time window and the voltage regulator is powered down on based on the determination that the second voltage exceeds the second voltage reference.

Abstract: A dynamic safe state control circuit is disclosed that controls an electrical motor based on vehicle speed. A microcontroller or other processing device is configured to control an inverter system of an electrical motor. The dynamic safe state control circuit is configured to receive a first signal that corresponds to a speed of the electric motor. The circuit is configured to activate any one of a plurality of safe states in the inverter system based on the first signal and in response to a malfunction in the microcontroller.

Abstract: An apparatus is disclosed that in one embodiment includes a circuit configured to selectively activate a transistor. The circuit is further configured to assert a signal when the circuit detects an electrical short between terminals of the transistor or when the circuit detects the transistor does not conduct current while the transistor is activated by the circuit. The circuit is further configured to output another signal, which is set to a first state or a second state. The other signal is set to the first state when the circuit detects the electrical short. The other signal is set to the second state when the circuit detects the transistor does not conduct current while activated.

Abstract: A system-on-a-chip (SoC) is designed to operate within optimal voltage and frequency ranges. If an SoC is provided power outside of the optimal voltage range, the SoC can be placed in a high-stress state, exposing the chip to a security attack. Embodiments of the present systems and method limit the minimum and maximum voltage supplied to an SoC from a power management integrated circuit (PMIC). Embodiments can also track a number of requests to provide power outside of the optimal range and can signal a warning of repeated attempts to take an SoC outside of the SoC's optimal range, which may be indicative of a malicious attack on the system.

Abstract: Various embodiments relate to a distributed power system, including: a primary power management integrated circuit (PMIC) configured to receive a source voltage and connected to a primary communication bus, wherein the primary PMIC produces a secondary voltage on a voltage line, wherein the primary PMIC communicates with a microcontroller unit (MCU) via the primary communication bus; and a plurality of secondary PMICs connected to the primary PMIC via the voltage line, a secondary communication bus, and a fail line, wherein the plurality of secondary PMICs are configured to produce a pulsed signal on the fail line when a secondary PMIC fails, wherein the pulsed signal produced by each of the plurality of secondary PMICs have a unique pulse width that indicates to the primary PMIC the identity of the failed secondary PMIC.

Abstract: Various embodiments relate to a distributed power system, including: a primary power management integrated circuit (PMIC) configured to receive a source voltage and connected to a primary communication bus, wherein the primary PMIC produces a secondary voltage on a voltage line, wherein the primary PMIC communicates with a microcontroller unit (MCU) via the primary communication bus; and a plurality of secondary PMICs connected to the primary PMIC via the voltage line, a secondary communication bus, and a fail line, wherein the plurality of secondary PMICs are configured to produce a pulsed signal on the fail line when a secondary PMIC fails, wherein the pulsed signal produced by each of the plurality of secondary PMICs have a unique pulse width that indicates to the primary PMIC the identity of the failed secondary PMIC.

Abstract: An apparatus to insure safe behavior in an inverter system. In one embodiment, the apparatus includes a first high side gate driver, a first low side gate driver, a microcontroller configured to control the first high side and low side gate drivers. A voltage regulator provides a supply voltage to the microcontroller. A first pair of high side voltage regulators provide a first pair of high side supply voltages to the first high side gate driver. A first pair of low side voltage regulators provide a first pair of low side supply voltages to the first low side gate driver.

Abstract: A dynamic safe state control circuit is disclosed that controls an electrical motor based on vehicle speed. A microcontroller or other processing device is configured to control an inverter system of an electrical motor. The dynamic safe state control circuit is configured to receive a first signal that corresponds to a speed of the electric motor. The circuit is configured to activate any one of a plurality of safe states in the inverter system based on the first signal and in response to a malfunction in the microcontroller.

Abstract: A system-on-a-chip (SoC) is designed to operate within optimal voltage and frequency ranges. If an SoC is provided power outside of the optimal voltage range, the SoC can be placed in a high-stress state, exposing the chip to a security attack. Embodiments of the present systems and method limit the minimum and maximum voltage supplied to an SoC from a power management integrated circuit (PMIC). Embodiments can also track a number of requests to provide power outside of the optimal range and can signal a warning of repeated attempts to take an SoC outside of the SoC's optimal range, which may be indicative of a malicious attack on the system.

Abstract: An apparatus is disclosed that in one embodiment includes a circuit configured to selectively activate a transistor. The circuit is further configured to assert a signal when the circuit detects an electrical short between terminals of the transistor or when the circuit detects the transistor does not conduct current while the transistor is activated by the circuit. The circuit is further configured to output another signal, which is set to a first state or a second state. The other signal is set to the first state when the circuit detects the electrical short. The other signal is set to the second state when the circuit detects the transistor does not conduct current while activated.

Abstract: An integrated circuit comprising: an input terminal configured to receive a failure-event-signal representative of a failure event; a first output terminal configured to provide a first-failure-signal; and a second output terminal configured to provide a second-failure-signal; and a processing block configured to: set the first-failure-signal based on the failure-event-signal; and set the second-failure-signal, at a predetermined time interval after the first-failure-signal is set. The processing block further comprises a switch configured selectively, based on a received digital-error-signal to either: set the second-failure-signal based on a digital-counter-output-signal; or set the second-failure-signal based on an analogue-trigger-signal.

Abstract: An integrated circuit comprising: an input terminal configured to receive a failure-event-signal representative of a failure event; a first output terminal configured to provide a first-failure-signal; and a second output terminal configured to provide a second-failure-signal; and a processing block configured to: set the first-failure-signal based on the failure-event-signal; and set the second-failure-signal, at a predetermined time interval after the first-failure-signal is set. The processing block further comprises a switch configured selectively, based on a received digital-error-signal to either: set the second-failure-signal based on a digital-counter-output-signal; or set the second-failure-signal based on an analogue-trigger-signal.

Abstract: A heating system is described for generating heat and bringing heat to a semiconductor device under test. The heating system comprises a conduction heating unit comprising a heating resistor, a thermal contact area for thermally contacting the semiconductor device under test, and a thermally conductive and electrically insulating connection between the heating resistor and the thermal contact area. The heating resistor is operable to generate a user-defined amount of heat and arranged to provide a part of the heat generated by the heating resistor to the thermal contact area via the thermally conductive and electrically insulating connection. It is also described that the heating system may further comprise a convection heating chamber operable to provide a user-defined heat-controlled convection to the semiconductor device under test. A method of testing a semiconductor device using a heating system is also described.

Abstract: A heating system is described for generating heat and bringing heat to a semiconductor device under test. The heating system comprises a conduction heating unit comprising a heating resistor, a thermal contact area for thermally contacting the semiconductor device under test, and a thermally conductive and electrically insulating connection between the heating resistor and the thermal contact area. The heating resistor is operable to generate a user-defined amount of heat and arranged to provide a part of the heat generated by the heating resistor to the thermal contact area via the thermally conductive and electrically insulating connection. It is also described that the heating system may further comprise a convection heating chamber operable to provide a user-defined heat-controlled convection to the semiconductor device under test. A method of testing a semiconductor device using a heating system is also described.