Abstract: A processor and method for concurrent processing of tasks and instructions are disclosed. The processor is basically a multiple instruction, multiple data stream (MIMD) digital computer that utilizes pipelining for control and function units, but avoids precedence constraint penalties. Task and instruction processing is carried on concurrently through the use of a snapshot taken of the next process status words (PSWs) to be serviced for each active task, the pointers for which are stored in task first in-first out buffers (task FIFOs). The PSWs, along with their parent task status words (TSWs), are placed into the control pipeline one at a time and serviced, after which each PSW pointer is placed back in the task FIFO from where it was taken. After all process status words of the snapshot have been entered into the control pipeline, a new snapshot is taken and the PSWs processed in the same manner.