Abstract: An adaptive variable length pulse synchronizer including a state keeper circuit, an asynchronous pulse edge detection circuit, a data synchronization circuit, and a pulse edge synchronization circuit. The state keeper circuit detects a leading edge of the asynchronous pulse. The asynchronous pulse edge detection circuit detects a trailing edge of the asynchronous pulse after the state keeper circuit has detected the leading edge. The asynchronous pulse edge detection circuit further provides a pulse synchronized with a clock signal after the asynchronous pulse has been detected. The data synchronization circuit latches the asynchronous data and provides the synchronous data in response to the synchronous pulse. The pulse edge synchronization provides the synchronous ready signal after synchronous data has been provided.

Abstract: Methods and corresponding systems for buffering an input signal include outputting a first logic value in response to the input signal being below a lower threshold. A second logic value is output in response to the input signal rising above the lower threshold. Thereafter, the second logic value is maintained until the input exceeds a higher threshold and thereafter falls below the higher threshold. In response to the input signal falling below the higher threshold, the first logic value is output, and maintained at the first logic value, until the input falls below the lower threshold and thereafter rises above the lower threshold.

Abstract: Methods and corresponding systems for buffering an input signal include outputting a first logic value in response to the input signal being below a lower threshold. A second logic value is output in response to the input signal rising above the lower threshold. Thereafter, the second logic value is maintained until the input exceeds a higher threshold and thereafter falls below the higher threshold. In response to the input signal falling below the higher threshold, the first logic value is output, and maintained at the first logic value, until the input falls below the lower threshold and thereafter rises above the lower threshold.

Abstract: In one form a circuit has a bias stage having an input signal terminal for receiving an input signal. The circuit modifies the input signal with a drive stage to provide an output signal in complement form. A drive transistor in the drive stage of the circuit has a bulk that is connected to a terminal of a load and to a control electrode coupled to the input signal terminal. A bias transistor in the bias stage of the circuit has a bulk that is directly connected to the terminal of the load and to the bulk of the drive transistor. The bias transistor has a control electrode coupled to the input signal terminal. The input signal biases the bulks of the drive transistor and the bias transistor and reduces transistor threshold voltage. Linearity of circuit output impedance is improved and RF interference reduced. Lower voltage operation is also provided.

Abstract: In one form a circuit has a bias stage having an input signal terminal for receiving an input signal. The circuit modifies the input signal with a drive stage to provide an output signal in complement form. A drive transistor in the drive stage of the circuit has a bulk that is connected to a terminal of a load and to a control electrode coupled to the input signal terminal. A bias transistor in the bias stage of the circuit has a bulk that is directly connected to the terminal of the load and to the bulk of the drive transistor. The bias transistor has a control electrode coupled to the input signal terminal. The input signal biases the bulks of the drive transistor and the bias transistor and reduces transistor threshold voltage. Linearity of circuit output impedance is improved and RF interference reduced. Lower voltage operation is also provided.

Abstract: An input voltage circuit comprises an input transistor having a control electrode for receiving a variable input voltage, a voltage detection transistor having a current electrode coupled to a current electrode of the input transistor forming a first node, and a current source coupled to a second current electrode of the voltage detection transistor forming a second node. The input voltage circuit further comprises a variable voltage drop transistor having a first current electrode coupled to the first node, a control electrode coupled to the second node and a second current electrode coupled to an output node, wherein the voltage detection transistor detects a variation in the variable input voltage and provides a signal to the variable voltage drop transistor. The variable voltage drop transistor generates a voltage drop proportional to the variation in the variable input voltage to ensure a substantially constant output at the output node.

Abstract: An input voltage circuit comprises an input transistor having a control electrode for receiving a variable input voltage, a voltage detection transistor having a current electrode coupled to a current electrode of the input transistor forming a first node, and a current source coupled to a second current electrode of the voltage detection transistor forming a second node. The input voltage circuit further comprises a variable voltage drop transistor having a first current electrode coupled to the first node, a control electrode coupled to the second node and a second current electrode coupled to an output node, wherein the voltage detection transistor detects a variation in the variable input voltage and provides a signal to the variable voltage drop transistor. The variable voltage drop transistor generates a voltage drop proportional to the variation in the variable input voltage to ensure a substantially constant output at the output node.

Abstract: A voltage regulator includes a first and second amplifier stage, an output stage, and a variable zero circuit. The first amplifier stage is coupled to receive a reference voltage and introduces a first pole of the voltage regulator. The second amplifier stage is coupled to the first amplifier stage and introduces a second pole of the voltage regulator. The output stage is coupled to the second amplifier stage, has an output driver, and is coupled to provide an output voltage based on the reference voltage. The variable zero circuit is coupled to the first amplifier stage, the second amplifier stage, and the output stage. The variable zero circuit provides a zero to compensate for at least one of the first pole or the second pole of the voltage regulator based on a gate to source voltage of the output driver and a drain to source voltage of the output driver.

Abstract: An adaptive variable length pulse synchronizer including a state keeper circuit, an asynchronous pulse edge detection circuit, a data synchronization circuit, and a pulse edge synchronization circuit. The state keeper circuit detects a leading edge of the asynchronous pulse. The asynchronous pulse edge detection circuit detects a trailing edge of the asynchronous pulse after the state keeper circuit has detected the leading edge. The asynchronous pulse edge detection circuit further provides a pulse synchronized with a clock signal after the asynchronous pulse has been detected. The data synchronization circuit latches the asynchronous data and provides the synchronous data in response to the synchronous pulse. The pulse edge synchronization provides the synchronous ready signal after synchronous data has been provided.

Abstract: An output buffer circuit (10, 40, 50) includes an output driver transistor (12), a predriver circuit (14, 54), and a bias generator (16, 54). The predriver circuit (14, 54) has an input terminal for receiving an input signal (IN), a first terminal coupled to a power supply voltage terminal, a second terminal, and an output terminal coupled to the control electrode of the transistor (12). The bias generator (16, 54) is coupled to the second terminal of the predriver circuit (14, 54), and provides a bias voltage (VG) to the second terminal of the predriver circuit (14, 54) for controlling the gate voltage of the output driver transistor (12).

Abstract: An output buffer circuit (10, 40, 50) includes an output driver transistor (12), a predriver circuit (14, 54), and a bias generator (16, 54). The predriver circuit (14, 54) has an input terminal for receiving an input signal (IN), a first terminal coupled to a power supply voltage terminal, a second terminal, and an output terminal coupled to the control electrode of the transistor (12). The bias generator (16, 54) is coupled to the second terminal of the predriver circuit (14, 54), and provides a bias voltage (VG) to the second terminal of the predriver circuit (14, 54) for controlling the gate voltage of the output driver transistor (12).

Abstract: A level shifter with cross coupled inverters having different threshold voltages. The output of the level shifter is pulled to a known voltage state during power up. In some examples, one of the inverters includes an additional N-channel transistor wherein the threshold voltage is greater the threshold voltage of the other inverter due to the additional transistor.

Abstract: A voltage regulator includes a first and second amplifier stage, an output stage, and a variable zero circuit. The first amplifier stage is coupled to receive a reference voltage and introduces a first pole of the voltage regulator. The second amplifier stage is coupled to the first amplifier stage and introduces a second pole of the voltage regulator. The output stage is coupled to the second amplifier stage, has an output driver, and is coupled to provide an output voltage based on the reference voltage. The variable zero circuit is coupled to the first amplifier stage, the second amplifier stage, and the output stage. The variable zero circuit provides a zero to compensate for at least one of the first pole or the second pole of the voltage regulator based on a gate to source voltage of the output driver and a drain to source voltage of the output driver.

Abstract: A level shifter with cross coupled inverters having different threshold voltages. The output of the level shifter is pulled to a known voltage state during power up. In some examples, one of the inverters includes an additional N-channel transistor wherein the threshold voltage is greater the threshold voltage of the other inverter due to the additional transistor.

Abstract: In a circuit including a number of functional blocks of circuits, each block having a minimum operating voltage, a plurality of sense lines from each of the blocks is used to measure local voltage fluctuation at each block. The power voltage(s) of the overall circuit may be globally regulating in the circuit responsive to such locally sensed voltage fluctuations to prevent the local voltages from dropping below the minimum operating voltage for each block.

Abstract: In a circuit including a number of functional blocks of circuits, each block having a minimum operating voltage, a plurality of sense lines from each of the blocks is used to measure local voltage fluctuations at each block. The power voltage(s) of the overall circuit may be globally regulated in the circuit responsive to such locally sensed voltage fluctuations to prevent the local voltages from dropping below the minimum operating voltage for each block.

Abstract: A method of reducing an equilibrium relative humidity level in an edible product comprising:applying a solution, incorporating a first humectant in a liquid form to the product whereby at least a part of the first humectant is absorbed into the edible product;applying a second humectant in a solid form to the product so as the second humectant absorbs residual moisture and is itself absorbed into the product; andwherein both the first and second humectants are effective in reducing the equilibrium relative humidity of the product to a predetermined level.