Patents by Inventor Mayan Riat

Mayan Riat has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9306776
    Abstract: A method for filtering a data signal includes transmitting the data signal from a transmitter to a receiver across a conductor disposed in an interposer, which interconnects the receiver and the transmitter. The data signal is low-passed with a filter, which includes a passive resistive element disposed within the interposer and coupled in series electrically with a passive inductive element. In relation thereto, the interposer is disposed in a position within the interposer, or upon a surface thereof. The filter is coupled to the conductor in a shunt configuration with respect to ground.
    Type: Grant
    Filed: September 10, 2013
    Date of Patent: April 5, 2016
    Assignee: NVIDIA CORPORATION
    Inventors: Yaping Zhou, Wenjie Mao, Huabo Chen, Mayan Riat
  • Publication number: 20150071333
    Abstract: A method for filtering a data signal includes transmitting the data signal from a transmitter to a receiver across a conductor disposed in an interposer, which interconnects the receiver and the transmitter. The data signal is low-passed with a filter, which includes a passive resistive element disposed within the interposer and coupled in series electrically with a passive inductive element. In relation thereto, the interposer is disposed in a position within the interposer, or upon a surface thereof. The filter is coupled to the conductor in a shunt configuration with respect to ground.
    Type: Application
    Filed: September 10, 2013
    Publication date: March 12, 2015
    Applicant: Nvidia Corporation
    Inventors: Yaping Zhou, Wenjie Mao, Huabo Chen, Mayan Riat
  • Publication number: 20140175619
    Abstract: An integrated circuit system includes an interposer substrate with an electrical reference plane, or “ground plane,” formed by a conductive semiconductor layer. The conductive semiconductor layer may be formed in a surface region of the interposer substrate, and in some embodiments is formed by performing an ion implant process on the surface region to increase the electrical conductivity of the surface region. Because the surface region is electrically coupled to an electrical ground of the integrated circuit system, the surface region functions as a ground plane that helps contain electric fields produced by signals routed through interconnects of the interposer substrate. Consequently, a ground plane can be formed on a surface of the interposer substrate without forming a metalization layer.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Applicant: NVIDIA CORPORATION
    Inventors: Abraham F. Yee, Mayan Riat