Abstract: An energetic composition and a method of unzipping polymer binders are disclosed, which includes localizing a heat feedback just near the reaction front by unzipping polymer binders employed to a nanothermite. The energetic composition includes an unzipping polymer binder employed to high load fuel and oxidizer particles.

Abstract: Computing devices and methods are used to detect and compensate for the presence of a cover layer on a touch input device. A computing device includes a processing device, a touch input device in electronic communication with the processing device, and a memory device in electronic communication with the processing device and having electronic instructions encoded thereon. The electronic instructions, when executed by the processing device, cause the processor to receive a first signal obtained from the touch input device over a first duration of time, the first signal including a first signal pattern, receive a second signal obtained from the touch input device over a second duration of time separate from the first duration of time, the second signal including a second signal pattern, determine a difference between the first signal pattern and the second signal pattern, and adjust a touch input detection setting based on the difference.

Abstract: Grip detection can be beneficial for an electronic device to ignore unintended contacts on a touch sensitive surface. Examples of the disclosure provide various ways for identifying an input patch as a grip. In some examples, identifying an input patch as a grip comprises determining whether the input patch satisfies one or more grip identification criteria. In some examples, identified grips are saved in a grip database. In some examples, the identified grips are filtered out of touch images. In some examples, when baseline touch data for a touch-sensitive is updated, the touch processor can forgo updating the baseline for portions of the touch sensitive surface associated with the identified grips.

Abstract: Computing devices and methods are used to detect and compensate for the presence of a cover layer on a touch input device. A computing device includes a processing device, a touch input device in electronic communication with the processing device, and a memory device in electronic communication with the processing device and having electronic instructions encoded thereon. The electronic instructions, when executed by the processing device, cause the processor to receive a first signal obtained from the touch input device over a first duration of time, the first signal including a first signal pattern, receive a second signal obtained from the touch input device over a second duration of time separate from the first duration of time, the second signal including a second signal pattern, determine a difference between the first signal pattern and the second signal pattern, and adjust a touch input detection setting based on the difference.

Abstract: Computing devices and methods are used to detect and compensate for the presence of a cover layer on a touch input device. A computing device includes a processing device, a touch input device in electronic communication with the processing device, and a memory device in electronic communication with the processing device and having electronic instructions encoded thereon. The electronic instructions, when executed by the processing device, cause the processor to receive a first signal obtained from the touch input device over a first duration of time, the first signal including a first signal pattern, receive a second signal obtained from the touch input device over a second duration of time separate from the first duration of time, the second signal including a second signal pattern, determine a difference between the first signal pattern and the second signal pattern, and adjust a touch input detection setting based on the difference.

Abstract: Methods, systems, and apparatus to facilitate multi-channel isolation is disclosed. An example apparatus includes a multiplexer including a first input terminal, a second input terminal, and an output terminal; a modulator including an input terminal and an output terminal, the input terminal of the modulator coupled to the output terminal of the multiplexer; an isolation capacitor including a first terminal and a second terminal, the first terminal of the isolation capacitor coupled to the output terminal of the modulator; a first receiver die coupled to the second terminal of the isolation capacitor; and a second receiver die coupled to the second terminal of the isolation capacitor.

Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.

Abstract: A bus repeater includes first and second bus ports, a first termination resistor network coupled to the first bus port, a second termination resistor network coupled to the second bus port, and a power state change detection circuit coupled to the second bus port. The power state change detection circuit is configured to detect a power state change initiated by a device coupled to the first bus port. The detection of the power state change includes a determination that a voltage on the second bus port exceeds a threshold. Responsive to detection of the power state change, the power state change detection circuit is configured cause a change in a configuration of at least one of the first or second termination resistor networks.

Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.

Abstract: Universal Serial Bus (USB) repeater circuits and methods of operating the same for communicating data signals from a first pair of data terminals to a second pair of data terminals of the repeater. In a first channel, an amplifier stage in a receiver amplifies a differential signal received at the first pair of data terminals to generate a differential signal at first and second output nodes of the receiver, and a transmitting circuit transmits a differential signal at the second pair of data terminals responsive to the differential signal at the first and second output nodes of the receiver. The receiver includes a hysteresis stage that receives an offset in opposition to the differential signal at the first and second output nodes of the receiver. End-of-packet (EOP) dribble in USB communications in the HS mode is reduced by the offset at the hysteresis stage.

Abstract: A synchronous serial bus peripheral circuit includes a peripheral identification (ID) register and a state machine circuit. The state machine circuit is coupled to the peripheral ID register, and is configured to transmit a status value based on a peripheral ID field of data received via the receiver shift register equaling a value stored in the peripheral ID register.

Abstract: A synchronous serial bus peripheral circuit includes a peripheral identification (ID) register and a state machine circuit. The state machine circuit is coupled to the peripheral ID register, and is configured to transmit a status value based on a peripheral ID field of data received via the receiver shift register equaling a value stored in the peripheral ID register.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed for a multi-level turn-off circuit. An example power delivery circuit includes a two-level turn-off circuit to be coupled to a first switch to reduce a first gate voltage of the first switch from a first voltage to a second voltage when a current flowing through the first switch is greater than an over-current threshold, the two-level turn-off circuit including a second switch, a voltage-current-voltage buffer to reduce a second gate voltage of the second switch from a third voltage to a fourth voltage, and a comparator circuit to turn off the second switch when the second gate voltage is the fourth voltage, and a driver to be coupled to the first switch to turn off the first switch when the second gate voltage is the fourth voltage.

Abstract: A bus repeater includes first and second bus ports, a first termination resistor network coupled to the first bus port, a second termination resistor network coupled to the second bus port, and a power state change detection circuit coupled to the second bus port. The power state change detection circuit is configured to detect a power state change initiated by a device coupled to the first bus port. The detection of the power state change includes a determination that a voltage on the second bus port exceeds a threshold. Responsive to detection of the power state change, the power state change detection circuit is configured cause a change in a configuration of at least one of the first or second termination resistor networks.

Abstract: An offset drift compensation circuit for correcting offset drift that changes with temperature. In one example, offset drift compensation circuit includes a low temperature offset compensation circuit and a high temperature offset circuit. The low temperature offset compensation circuit is configured to compensate for drift in offset at a first rate below a selected temperature. The high temperature offset compensation circuit is configured to compensate for drift in offset at a second rate above the selected temperature. The first rate is different from the second rate.

Abstract: A method of forming a void, channel and/or vascular network in a polymeric matrix comprises providing a pre-vascularized structure that includes a matrix material and a sacrificial material embedded in the matrix material in a predetermined pattern, where the matrix material comprises a monomer and the sacrificial material comprises a polymer. A region of the matrix material is activated to initiate an exothermic polymerization reaction and generate a self-propagating polymerization front. As the polymerization front propagates through the matrix material and polymerizes the monomer, heat from the exothermic reaction simultaneously degrades the sacrificial material into a gas-phase and/or liquid-phase byproduct. Thus, one or more voids or channels having the predetermined pattern are rapidly formed in the matrix material.

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.

Abstract: Grip detection can be beneficial for an electronic device to ignore unintended contacts on a touch sensitive surface. Examples of the disclosure provide various ways for identifying an input patch as a grip. In some examples, identifying an input patch as a grip comprises determining whether the input patch satisfies one or more grip identification criteria. In some examples, identified grips are saved in a grip database. In some examples, the identified grips are filtered out of touch images. In some examples, when baseline touch data for a touch-sensitive is updated, the touch processor can forgo updating the baseline for portions of the touch sensitive surface associated with the identified grips.

Abstract: A serial bus equalization trim circuit includes a first data input terminal, a second data input terminal, a delay circuit, and a flip-flop. The delay circuit includes a data input, a trim input, and an output. The data input is coupled the first data input terminal. The flip-flop includes a data input, a clock input, and an output. The data input is coupled to the output of the delay circuit. The clock input is coupled to the second data input terminal. The output is coupled to the trim input of the delay circuit.

Abstract: A circuit includes signal conditioner circuitry, level shifter circuitry, and state detector and controller circuitry coupled between the signal conditioner circuitry and the level shifter circuitry. The state detector and controller circuitry includes receiver circuitry and a finite state machine coupled to the receiver circuitry. The finite state machine is configured to detect a first data rate from signals, control operation of the signal conditioner circuitry responsive to detecting the first data rate, and control operation of the level shifter circuitry during a second data rate.