Patents by Inventor Mayukh Bhattacharya
Mayukh Bhattacharya has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240061035Abstract: A method of determining defect sensitization includes parsing a netlist of a circuit design to determine a plurality of potential defects and partitioning the circuit design into a plurality of blocks. The method also includes generating a graph representing the circuit design and determining a transitive closure of the graph. The method further includes grouping the plurality of potential defects to produce a plurality of groups of potential defects and selecting a potential defect from each group of the plurality of groups to form a simulation group of potential defects. The method also includes simulating the circuit design by injecting, into the circuit design, every potential defect of the simulation group to produce a set of outputs of the plurality of blocks and determining a defect sensitization for the simulation group of potential defects based on the set of outputs of the plurality of blocks.Type: ApplicationFiled: November 29, 2022Publication date: February 22, 2024Inventors: Mayukh BHATTACHARYA, Jonti TALUKDAR, Shan YUAN, Huiping HUANG
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Patent number: 11797737Abstract: This disclosure describes a method for finding equivalent classes of hard defects in a stacked MOSFET array. The method includes identifying the stacked MOSFET array in a circuit netlist. The stacked MOSFET array includes standard MOSFETs sharing gate and bulk terminals. The method further includes determining electrical defects for the standard MOSFETs, grouping the electrical defects into at least one intermediate equivalent defect class based on a topological equivalence of the electrical defects, grouping the electrical defects in the at least one intermediate equivalent defect class into at least one final equivalent defect class based on an electrical equivalence of the electrical defects, performing a defect simulation on an electrical defect in the at least one final equivalent defect class, and attributing a result of the defect simulation on the electrical defect to additional electrical defects in the final equivalent defect class.Type: GrantFiled: August 12, 2021Date of Patent: October 24, 2023Assignee: Synopsys, Inc.Inventors: Mayukh Bhattacharya, Michal Jerzy Rewienski, Shan Yuan, Michael Durr, Chih Ping Antony Fan
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Patent number: 11763056Abstract: A method of simulating defects in an analog circuit design includes, in part, defining a multitude of defect models, defining a defect scope associated with the defect models, and compiling, by a processor, the defect models, the defect scope, and a netlist associated with the analog circuit design. The method further includes, in part, scanning the netlist to identify a multitude of nodes to which a multitude of defects defined by the defect models and the defect scope are applied, injecting the multitude of defects at the identified nodes, and simulating the analog circuit design using the injected defects.Type: GrantFiled: April 20, 2021Date of Patent: September 19, 2023Assignee: Synopsys, Inc.Inventors: Mayukh Bhattacharya, Michael Durr, Mira Tzakova, Beatrice Solignac, Rayson Yam
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Patent number: 11734482Abstract: In one aspect, a transistor-level description of a circuit is accessed, where the circuit includes a plurality of transistors. A transistor-level circuit simulation of the circuit's response to an input stimulus is performed, based on the transistor-level description of the circuit. Activity levels for the transistors in the circuit are determined from the transistor-level circuit simulation. A graphical representation of the circuit is rendered. The graphical representation contains graphical elements that represent components of the circuit, and the graphical elements are visually coded according to the activity levels of the transistors in the corresponding components.Type: GrantFiled: November 9, 2021Date of Patent: August 22, 2023Assignee: Synopsys, Inc.Inventors: Mayukh Bhattacharya, Aleksandrs Krjukovs, Chih-Ping Antony Fan
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Patent number: 11669667Abstract: Systems and methods for automatic test pattern generation (ATPG) for parametric faults are described. A model may be constructed to predict a measurement margin for an integrated circuit (IC) design based on a random sample of random variables. A set of failure events may be determined for the IC design using the model, where each failure event may correspond to a set of values of the random variables that is expected to cause a metric for the IC design to violate a threshold.Type: GrantFiled: February 19, 2021Date of Patent: June 6, 2023Assignee: Synopsys, Inc.Inventors: Peilin Jiang, Mayukh Bhattacharya, Chih Ping Antony Fan
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Patent number: 11620424Abstract: A system and method utilized to receive an integrated circuit (IC) design and generating a graph based on a plurality of sub-circuits of the IC design. Further, one or more candidate sub-circuits are determined from the plurality of sub-circuits based on the graph. Additionally, one or more sub-circuits are identified from the one or more candidate sub-circuits based on a number of transistors and a number of edges within each of the plurality of sub-circuits. An indication of the identified one or more sub-circuits is provided.Type: GrantFiled: October 14, 2021Date of Patent: April 4, 2023Assignee: Synopsys, Inc.Inventors: Mayukh Bhattacharya, Sayandeep Sanyal, Amit Patra, Pallab Dasgupta
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Patent number: 11579994Abstract: A system and method of detecting defects in an analog circuit is provided. A method includes identifying a channel connected block (CCB) from a netlist, creating defect for the CCB to be injected during a simulation, obtaining a first measurement of an output node of the CCB by performing a first analog circuit simulation for the CCB based on providing excitations as inputs to the CCB and obtaining a second measurement of the output node of the CCB by performing a second analog circuit simulation for the CCB based on providing the excitations as the inputs to the CCB and injecting the defect. The method can further include determining a defect type based on the first measurement and the second measurement.Type: GrantFiled: April 15, 2021Date of Patent: February 14, 2023Assignee: Synopsys, Inc.Inventors: Mayukh Bhattacharya, Huiping Huang, Antony Fan
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Patent number: 11443092Abstract: A method, apparatus, and/or computer program product can perform an analog defect simulation on an electronic device. The method, apparatus, and/or computer program product can generate a defect catalog which identifies a defect class relating to a defect and a modeling parameter that is associated with the defect class. The method, apparatus, and/or computer program product can receive a weight formula that identifies a weight for the defect class in relation to the modeling parameter. The method, apparatus, and/or computer program product can call a defect weight function to return the weight from the defect weight formula. The method, apparatus, and/or computer program product can perform the analog defect simulation on the electronic device. The method, apparatus, and/or computer program product can determine a simulation statistic relating to the analog defect simulation utilizing the weight.Type: GrantFiled: May 11, 2020Date of Patent: September 13, 2022Assignee: Synopsys, Inc.Inventors: Mayukh Bhattacharya, Miroslava Tzakova, Chih-Ping Antony Fan
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Patent number: 11361135Abstract: A method of evaluating sampling sizes for circuit simulation comprises generating a plurality of coverage scenarios based on a defect universe, determining a coverage amount for each of the plurality of coverage scenarios, and associating the plurality of coverage scenarios with a plurality of bins based on the coverage amount for each of the plurality of coverage scenarios. The method further comprises sampling, with a first sampling size, each of the coverage scenarios to determine first sampled coverage scenarios, and determining an error value for each of the plurality of coverage scenarios based on the coverage amount of each of the plurality of coverage scenarios and a coverage amount of a respective one of the first sampled coverage scenarios.Type: GrantFiled: June 4, 2021Date of Patent: June 14, 2022Assignee: Synopsys, Inc.Inventors: Mayukh Bhattacharya, Mihir Sherlekar, Antony Fan
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Publication number: 20220121799Abstract: A system and method utilized to receive an integrated circuit (IC) design and generating a graph based on a plurality of sub-circuits of the IC design. Further, one or more candidate sub-circuits are determined from the plurality of sub-circuits based on the graph. Additionally, one or more sub-circuits are identified from the one or more candidate sub-circuits based on a number of transistors and a number of edges within each of the plurality of sub-circuits. An indication of the identified one or more sub-circuits is provided.Type: ApplicationFiled: October 14, 2021Publication date: April 21, 2022Inventors: Mayukh BHATTACHARYA, Sayandeep SANYAL, Amit PATRA, Pallab DASGUPTA
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Publication number: 20210383047Abstract: A method of evaluating sampling sizes for circuit simulation comprises generating a plurality of coverage scenarios based on a defect universe, determining a coverage amount for each of the plurality of coverage scenarios, and associating the plurality of coverage scenarios with a plurality of bins based on the coverage amount for each of the plurality of coverage scenarios. The method further comprises sampling, with a first sampling size, each of the coverage scenarios to determine first sampled coverage scenarios, and determining an error value for each of the plurality of coverage scenarios based on the coverage amount of each of the plurality of coverage scenarios and a coverage amount of a respective one of the first sampled coverage scenarios.Type: ApplicationFiled: June 4, 2021Publication date: December 9, 2021Inventors: Mayukh BHATTACHARYA, Mihir SHERLEKAR, Antony FAN
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Publication number: 20210374313Abstract: This disclosure describes a method for finding equivalent classes of hard defects in a stacked MOSFET array. The method includes identifying the stacked MOSFET array in a circuit netlist. The stacked MOSFET array includes standard MOSFETs sharing gate and bulk terminals. The method further includes determining electrical defects for the standard MOSFETs, grouping the electrical defects into at least one intermediate equivalent defect class based on a topological equivalence of the electrical defects, grouping the electrical defects in the at least one intermediate equivalent defect class into at least one final equivalent defect class based on an electrical equivalence of the electrical defects, performing a defect simulation on an electrical defect in the at least one final equivalent defect class, and attributing a result of the defect simulation on the electrical defect to additional electrical defects in the final equivalent defect class.Type: ApplicationFiled: August 12, 2021Publication date: December 2, 2021Applicant: Synopsys, Inc.Inventors: Mayukh BHATTACHARYA, Michal Jerzy REWIENSKI, Shan YUAN, Michael DURR, Chih Ping Antony FAN
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Publication number: 20210350058Abstract: A method, apparatus, and/or computer program product can performing an analog defect simulation on an electronic device. The method, apparatus, and/or computer program product can generate a defect catalog which identifies a defect class relating to a defect and a modeling parameter that is associated with the defect class. The method, apparatus, and/or computer program product can receive a weight formula that identifies a weight for the defect class in relation to the modeling parameter. The method, apparatus, and/or computer program product can call a defect weight function to return the weight from the defect weight formula. The method, apparatus, and/or computer program product can perform the analog defect simulation on the electronic device. The method, apparatus, and/or computer program product can determine a simulation statistic relating to the analog defect simulation utilizing the weight.Type: ApplicationFiled: May 11, 2020Publication date: November 11, 2021Applicant: Synopsys, Inc.Inventors: Mayukh BHATTACHARYA, Miroslava TZAKOVA, Chih-Ping Antony FAN
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Publication number: 20210326506Abstract: A method of simulating defects in an analog circuit design includes, in part, defining a multitude of defect models, defining a defect scope associated with the defect models, and compiling, by a processor, the defect models, the defect scope, and a netlist associated with the analog circuit design. The method further includes, in part, scanning the netlist to identify a multitude of nodes to which a multitude of defects defined by the defect models and the defect scope are applied, injecting the multitude of defects at the identified nodes, and simulating the analog circuit design using the injected defects.Type: ApplicationFiled: April 20, 2021Publication date: October 21, 2021Inventors: Mayukh Bhattacharya, Michael Durr, Mira Tzakova, Beatrice Solignac, Rayson Yam
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Publication number: 20210326227Abstract: A system and method of detecting defects in an analog circuit is provided. A method includes identifying a channel connected block (CCB) from a netlist, creating defect for the CCB to be injected during a simulation, obtaining a first measurement of an output node of the CCB by performing a first analog circuit simulation for the CCB based on providing excitations as inputs to the CCB and obtaining a second measurement of the output node of the CCB by performing a second analog circuit simulation for the CCB based on providing the excitations as the inputs to the CCB and injecting the defect. The method can further include determining a defect type based on the first measurement and the second measurement.Type: ApplicationFiled: April 15, 2021Publication date: October 21, 2021Applicant: Synopsys, Inc.Inventors: Mayukh Bhattacharya, Huiping Huang, Antony Fan
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Patent number: 11141777Abstract: A method is used to manufacture a surgical instrument configured to apply a surgical clip to a patient. The surgical instrument includes a jaw retaining assembly. The jaw retaining assembly includes a shaft and opposing first and second jaws. The method includes metal injection molding a first metallic portion of the jaw retaining assembly. The method also includes metal injection molding, stamping, and/or laser cutting a second metallic portion of the jaw retaining assembly, wherein the second metallic portion is separately formed from the first metallic portion. The method also includes fixably coupling the first and second metallic portions of the jaw retaining assembly together.Type: GrantFiled: December 31, 2018Date of Patent: October 12, 2021Assignee: Cilag GmbH InternationalInventors: Anil K. Nalagatla, Frederick E. Shelton, IV, Chester O. Baxter, III, Amit Gupta, Mayukh Bhattacharya
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Publication number: 20210312113Abstract: In modern VLSI technology, often, stacked arrays of smaller sized MOSFETs are used to achieve the desired width and length of a design MOSFET. In analog defect simulation, each physical transistor can contribute to the circuit's defect universe and this can directly lead to tremendous increase in defect simulation time. Here we propose a method of finding equivalent defects in the context of stacked MOSFET arrays that can lead to significant reduction in defect simulation effort and yet provide accurate defect coverage results.Type: ApplicationFiled: April 2, 2021Publication date: October 7, 2021Applicant: Synopsys, Inc.Inventors: Mayukh BHATTACHARYA, Michal Jerzy Rewienski, Shan Yuan, Michael Durr, Chih Ping Antony Fan
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Publication number: 20210264087Abstract: Systems and methods for automatic test pattern generation (ATPG) for parametric faults are described. A model may be constructed to predict a measurement margin for an integrated circuit (IC) design based on a random sample of random variables. A set of failure events may be determined for the IC design using the model, where each failure event may correspond to a set of values of the random variables that is expected to cause a metric for the IC design to violate a threshold.Type: ApplicationFiled: February 19, 2021Publication date: August 26, 2021Applicant: Synopsys, Inc.Inventors: Peilin Jiang, Mayukh Bhattacharya, Chih Ping Antony Fan
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Publication number: 20200206805Abstract: A method is used to manufacture a surgical instrument configured to apply a surgical clip to a patient. The surgical instrument includes a jaw retaining assembly. The jaw retaining assembly includes a shaft and opposing first and second jaws. The method includes metal injection molding a first metallic portion of the jaw retaining assembly. The method also includes metal injection molding, stamping, and/or laser cutting a second metallic portion of the jaw retaining assembly, wherein the second metallic portion is separately formed from the first metallic portion. The method also includes fixably coupling the first and second metallic portions of the jaw retaining assembly together.Type: ApplicationFiled: December 31, 2018Publication date: July 2, 2020Inventors: Anil K. Nalagatla, Frederick E. Shelton, IV, Chester O. Baxter, III, Amit Gupta, Mayukh Bhattacharya
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Patent number: 10409941Abstract: A circuit description, such as a hierarchical netlist, is obtained for an integrated circuit. Based on the circuit description, a treemap representation is rendered using blocks, nodes, and/or devices from the hierarchical netlist as objects, or leaves, in the treemap representation. Using a virtual layout, the leaves are positioned in the treemap representation independent of their physical layout. Circuit properties for the electronic design are also obtained using various methods such as a circuit simulator. The circuit properties are displayed to a user on the treemap representation.Type: GrantFiled: October 31, 2013Date of Patent: September 10, 2019Assignee: SYNOPSYS, INC.Inventors: Mayukh Bhattacharya, Chih-Ping Antony Fan, Huiping Huang, Vinay Nulkar, Amelia Huimin Shen