Patents by Inventor Mayuresh Patki

Mayuresh Patki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240170867
    Abstract: A connector for electrically connecting to conductive structures formed on a semiconductor device includes a core with first, second and third ground planes isolated from each other and signal vias and ground vias formed therein, conductive signal traces formed coplanar with the second ground plane and isolated from a conductive ground layer forming the second ground plane, where one or more conductive signal traces are shielded by the conductive ground layer and by the first and third ground planes. The connector includes a first set of contact elements electrically connected to signal vias that are electrically connected to first ends of the conductive signal traces and a second set of contact elements electrically connected to signal vias that are electrically connected to second ends of the conductive signal traces.
    Type: Application
    Filed: January 30, 2024
    Publication date: May 23, 2024
    Inventors: Woody Maynard, Mayuresh Patki, David Chen, Gary Hsieh
  • Patent number: 11967782
    Abstract: A connector for electrically connecting to conductive structures formed on a semiconductor device includes a core including an isolation layer and signal vias and ground vias formed in the isolation layer; a first ground plane formed on a surface of or in the core and electrically connected to the ground vias; a first set of contact elements formed on a first surface of the core and electrically connected to the signal vias to form signal pins; a second set of contact elements formed on the first surface and electrically connected to a subset of the ground vias to form ground pins. The remaining ground vias without contact elements form buried ground vias. The first and second sets of contact elements are arranged on the first surface of the core to surround each signal pin by at least one adjacent ground pin and one or more adjacent buried ground vias.
    Type: Grant
    Filed: October 6, 2021
    Date of Patent: April 23, 2024
    Assignee: Neoconix, Inc.
    Inventors: Woody Maynard, Mayuresh Patki, David Chen, Gary Hsieh
  • Publication number: 20220149550
    Abstract: A connector for electrically connecting to conductive structures formed on a semiconductor device includes a core including an isolation layer and signal vias and ground vias formed in the isolation layer; a first ground plane formed on a surface of the core and electrically connected to the ground vias; a first set of contact elements formed on a first surface of the core and electrically connected to the signal vias to form signal pins; a second set of contact elements formed on the first surface and electrically connected to a subset of the ground vias to form ground pins. The remaining ground vias without contact elements form buried ground vias. The first and second sets of contact elements are arranged on the first surface of the core to surround each signal pin by at least one adjacent ground pin and one or more adjacent buried ground vias.
    Type: Application
    Filed: October 6, 2021
    Publication date: May 12, 2022
    Inventors: Woody Maynard, Mayuresh Patki, David Chen, Gary Hsieh