Patents by Inventor MAZYAR RAZZAZ

MAZYAR RAZZAZ has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10366005
    Abstract: Methods and systems for accessing a memory are provided. One method of accessing a memory includes generating a memory access profile for accesses to a memory array. A memory controller coupled to the memory array is configured using the generated memory access profile. After configuring the memory controller, accesses to the memory array are interleaved based on the memory access profile.
    Type: Grant
    Filed: May 20, 2016
    Date of Patent: July 30, 2019
    Assignee: NXP USA, INC.
    Inventors: Arup Chakraborty, Mazyar Razzaz, James A. Welker
  • Publication number: 20170336973
    Abstract: Methods and systems for accessing a memory are provided. One method of accessing a memory includes generating a memory access profile for accesses to a memory array. A memory controller coupled to the memory array is configured using the generated memory access profile. After configuring the memory controller, accesses to the memory array are interleaved based on the memory access profile.
    Type: Application
    Filed: May 20, 2016
    Publication date: November 23, 2017
    Inventors: Arup Chakraborty, MAZYAR RAZZAZ, JAMES A. WELKER
  • Patent number: 9437326
    Abstract: A tool for testing a double data rate (“DDR”) memory controller to ensure that data strobe transitions are aligned with data eyes to achieve a desired data integrity during data transfers between the memory controller and the memories. After the memory controller completes its training sequence during the initialization process, the tool sweeps the data strobe transition across the data eye. At each timing step during the sweep, several tests may be conducted to check for integrity of functionality. The tool thus generates a pass/fail margin table. The locations of the data strobe transitions selected by the memory controller during its previously run training sequence are then added to this tool-generated margin table. The result is essentially a pseudo data eye, reconstructed including the data strobe transition with the data eye.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: September 6, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Mazyar Razzaz, Kenneth R. Burch, James A. Welker
  • Publication number: 20150364212
    Abstract: A tool for testing a double data rate (“DDR”) memory controller to ensure that data strobe transitions are aligned with data eyes to achieve a desired data integrity during data transfers between the memory controller and the memories. After the memory controller completes its training sequence during the initialization process, the tool sweeps the data strobe transition across the data eye. At each timing step during the sweep, several tests may be conducted to check for integrity of functionality. The tool thus generates a pass/fail margin table. The locations of the data strobe transitions selected by the memory controller during its previously run training sequence are then added to this tool-generated margin table. The result is essentially a pseudo data eye, reconstructed including the data strobe transition with the data eye.
    Type: Application
    Filed: June 12, 2014
    Publication date: December 17, 2015
    Inventors: MAZYAR RAZZAZ, KENNETH R. BURCH, JAMES A. WELKER