Patents by Inventor Md Altaf HOSSAIN
Md Altaf HOSSAIN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230112097Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.Type: ApplicationFiled: December 12, 2022Publication date: April 13, 2023Applicant: Tahoe Research, Ltd.Inventors: MD Altaf HOSSAIN, Scott A. GILBERT
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Publication number: 20230107106Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.Type: ApplicationFiled: December 12, 2022Publication date: April 6, 2023Inventors: MD Altaf HOSSAIN, Ankireddy NALAMALPU, Dheeraj SUBBAREDDY, Robert SANKMAN, Ravindranath V. MAHAJAN, Debendra MALLIK, Ram S. VISWANATH, Sandeep B. SANE, Sriram SRINIVASAN, Rajat AGARWAL, Aravind DASU, Scott WEBER, Ravi GUTALA
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Patent number: 11610856Abstract: An integrated circuit package may be formed comprising an interposer with a center die and a plurality of identical integrated circuit dice positioned around the center die and attached to the interposer, wherein the center die is the switch/router for the plurality of identical integrated circuit dice. The interposer comprises a substrate, a central pattern of bond pads formed in or on the substrate for attaching the center die, and substantially identical satellite patterns formed in or on the substrate for attaching identical integrated circuit dice. The central pattern of bond pads has repeating sets of a specific geometric pattern and wherein the identical satellite patterns of bond pads are positioned to form the same geometric pattern as the specific geometric pattern of the central pattern of bond pads. Thus, substantially identical conductive routes may be formed between the center die and each of the identical integrated circuit dice.Type: GrantFiled: June 24, 2019Date of Patent: March 21, 2023Assignee: Intel CorporationInventors: Robert Sankman, Dheeraj Subbareddy, Md Altaf Hossain, Ankireddy Nalamalpu
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Patent number: 11595045Abstract: A programmable device may have logic circuitry formed in a top die and memory and specialized processing blocks formed in a bottom die, where the top die is stacked directly on top of the bottom die in a face-to-face configuration. The logic circuitry may include logic sectors, logic array blocks, logic elements, and other types of logic regions. The memory blocks may include large banks of multiport memory for storing data. The specialized processing blocks may include multipliers, adders, and other arithmetic components. The logic circuitry may access the memory and specialized processing blocks via an address encoded scheme. Configured in this way, the maximum operating frequency of the programmable device can be optimized such that critical paths will no longer need to traverse any unused memory and specialized processing blocks.Type: GrantFiled: June 25, 2021Date of Patent: February 28, 2023Assignee: Intel CorporationInventors: Dheeraj Subbareddy, MD Altaf Hossain, Ankireddy Nalamalpu, Robert Sankman, Ravindranath Mahajan, Gregg William Baeckler
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Publication number: 20230049681Abstract: An integrated circuit die includes input buffer circuits that are enabled during an input mode of operation in response to first control signals to transmit input signals into the integrated circuit die from conductive bumps. Each of the input buffer circuits is coupled to one of the conductive bumps. The integrated circuit die also includes output buffer circuits that are each coupled to one of the conductive bumps. The output buffer circuits are enabled during an output mode of operation in response to second control signals to transmit output signals from the integrated circuit die to the conductive bumps. The input buffer circuits are disabled from transmitting signals during the output mode of operation in response to the first control signals. The output buffer circuits are disabled from transmitting signals during the input mode of operation in response to the second control signals.Type: ApplicationFiled: October 25, 2022Publication date: February 16, 2023Applicant: Intel CorporationInventors: Jeffrey Chromczak, Chooi Pei Lim, Lai Guan Tang, Chee Hak Teh, MD Altaf Hossain, Dheeraj Subbareddy, Ankireddy Nalamalpu
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Publication number: 20230035058Abstract: A circuit system includes a first integrated circuit and a second integrated circuit that includes a boot management controller circuit. The boot management controller circuit provides boot code to the first integrated circuit in response to the circuit system powering up. The first integrated circuit performs a boot operation using the boot code received from the boot management controller circuit.Type: ApplicationFiled: September 28, 2022Publication date: February 2, 2023Applicant: Intel CorporationInventors: Md Altaf Hossain, Mahesh Kumashikar, Ankireddy Nalamalpu, Sreedhar Ravipalli
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Publication number: 20230024515Abstract: A programmable logic device may include a first layer formed using backside metallization on a back plane of the programmable logic device and a second fabric routing circuitry to route second data within the programmable fabric. The first layer may include first fabric routing circuitry to route first data within a programmable fabric of the programmable logic device, and clock routing circuitry to route clock signals within the programmable fabric.Type: ApplicationFiled: September 30, 2022Publication date: January 26, 2023Inventors: Atul Maheshwari, Mahesh K. Kumashikar, Ankireddy Nalamalpu, MD Altaf Hossain, Mahesh A. Iyer
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Publication number: 20230018793Abstract: A processing integrated circuit includes a processing core comprising hard logic circuits and a programmable interface circuit configurable to exchange signals between an external terminal of the processing integrated circuit and the hard logic circuits in the processing core.Type: ApplicationFiled: September 22, 2022Publication date: January 19, 2023Applicant: Intel CorporationInventors: Md Altaf Hossain, Mahesh Kumashikar, Ankireddy Nalamalpu, Sreedhar Ravipalli
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Patent number: 11557541Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises, a package substrate, an interposer on the package substrate, a first die cube and a second die cube on the interposer, wherein the interposer includes conductive traces for electrically coupling the first die cube to the second die cube, a die on the package substrate, and an embedded multi-die interconnect bridge (EMIB) in the package substrate, wherein the EMIB electrically couples the interposer to the die.Type: GrantFiled: December 28, 2018Date of Patent: January 17, 2023Assignee: Intel CorporationInventors: Md Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy, Robert Sankman, Ravindranath V. Mahajan, Debendra Mallik, Ram S. Viswanath, Sandeep B. Sane, Sriram Srinivasan, Rajat Agarwal, Aravind Dasu, Scott Weber, Ravi Gutala
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Patent number: 11538753Abstract: An electronic chip, system, and method includes a power block including a power source configured to provide power to components of the electronic chip and a relay circuit coupled to the power source and a ground plane. The electronic chip further includes chip package having a first major side and a second major side, the power block secured to the second major side, the chip package comprising electrical connections, disposed on the second major side, to be secured with respect to a circuit board, and interconnect circuitry, electrically coupling the power block to ground, comprising a plurality of conductive layers, a conductive through hole, electrically connecting a first pair of the plurality of conductive layers, having a first width, and a via, electrically connecting a second pair of the plurality of conductive layers, having a second width less than the first width.Type: GrantFiled: December 30, 2016Date of Patent: December 27, 2022Assignee: Intel CorporationInventors: MD Altaf Hossain, Ankireddy Nalamalpu, Scott Gilbert, Jin Zhao
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Patent number: 11528809Abstract: A BGA structure having larger solder balls in high stress regions of the array is disclosed. The larger solder balls have higher solder joint reliability (SJR) and as such may be designated critical to function (CTF), whereby the larger solder balls in high stress regions carry input/output signals between a circuit board and a package mounted thereon. The larger solder balls are accommodated by recessing each ball in the package substrate, the circuit board, or both the package substrate and the circuit board. Additionally, a ball attach method for mounting a plurality of solder balls having different average diameters is disclosed.Type: GrantFiled: February 26, 2021Date of Patent: December 13, 2022Assignee: Tahoe Research, Ltd.Inventors: Md Altaf Hossain, Scott A. Gilbert
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Patent number: 11500412Abstract: A circuit system includes an interposer that has a first clock network and first and second integrated circuit dies that are mounted on the interposer. The first integrated circuit die includes a phase detector circuit, an adjustable delay circuit that generates a second clock signal in response to a first clock signal received from the first clock network, and a second clock network that generates a third clock signal in response to the second clock signal. The second integrated circuit die comprises a third clock network that generates a fourth clock signal in response to the first clock signal received from the first clock network. The phase detector circuit controls a delay provided by the adjustable delay circuit to the second clock signal based on a phase comparison between phases of the third and fourth clock signals.Type: GrantFiled: March 28, 2019Date of Patent: November 15, 2022Assignee: Intel CorporationInventors: Jeffrey Chromczak, Chooi Pei Lim, Lai Guan Tang, Chee Hak Teh, MD Altaf Hossain, Dheeraj Subbareddy, Ankireddy Nalamalpu
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Publication number: 20220334983Abstract: A circuit system includes a processing integrated circuit die comprising a first die-to-die interface circuit and a memory interface circuit. The circuit system also includes a second integrated circuit die comprising a second die-to-die interface circuit and a compute circuit that performs computations for the processing integrated circuit die. The first and the second die-to-die interface circuits are coupled together. The compute circuit is coupled to exchange information with the memory interface circuit through the first and the second die-to-die interface circuits.Type: ApplicationFiled: June 28, 2022Publication date: October 20, 2022Applicant: Intel CorporationInventors: Mahesh Kumashikar, Md Altaf Hossain, Ankireddy Nalamalpu, Sreedhar Ravipalli
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Publication number: 20220334979Abstract: An integrated circuit includes logic circuits, first buffer circuits coupled to external ports of the integrated circuit, second buffer circuits that are each coupled to one of the logic circuits, and a crossbar circuit coupled to the first and the second buffer circuits. The crossbar circuit is configurable to provide data transfer between the logic circuits and the external ports of the integrated circuit through the first buffer circuits and the second buffer circuits.Type: ApplicationFiled: June 29, 2022Publication date: October 20, 2022Applicant: Intel CorporationInventors: Sreedhar Ravipalli, Mahesh Kumashikar, Md Altaf Hossain, Ankireddy Nalamalpu
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Publication number: 20220337248Abstract: Systems, methods, and devices are provided for configurable die-to-die communication between dies of an integrated circuit system using a programmable routing bridge. Such an integrated circuit system may include a first die on a substrate, a second die on the substrate, and a programmable routing bridge embedded in the substrate. The programmable routing bridge may be mounted to the first die and the second die and is configurable to transfer data between selectable points of the first die and selectable points of the second die.Type: ApplicationFiled: July 1, 2022Publication date: October 20, 2022Inventors: J-Wing Teh, Min Suet Lim, Lai Guan Tang, MD Altaf Hossain, Gregory Steinke
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Publication number: 20220334630Abstract: A circuit system includes an accelerator circuit and a compute circuit. The accelerator circuit generates a request in response to receiving packets of data. The accelerator circuit generates an indication of a low power state based on a reduced number of the packets of data being received. The compute circuit performs a processing operation for the accelerator circuit using the packets of data in response to receiving the request. The compute circuit comprises a power management circuit that decreases a supply voltage in the compute circuit and decreases a frequency of a clock signal in the compute circuit in response to the indication of the low power state from the accelerator circuit.Type: ApplicationFiled: June 25, 2022Publication date: October 20, 2022Applicant: Intel CorporationInventors: Sreedhar Ravipalli, Mahesh Kumashikar, Md Altaf Hossain, Ankireddy Nalamalpu
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Patent number: 11476185Abstract: Embodiments of the invention include a stacked die system and methods for forming such systems. In an embodiment, the stacked die system may include a first die. The first die may include a device layer and a plurality of routing layers formed over the device layer. The plurality of routing layers may be segmented into a plurality of sub regions. In an embodiment no conductive traces in the plurality of routing layers pass over a boundary between any of the plurality of sub regions. In an embodiment, the stacked die system may also include a plurality of second dies stacked over the first die. According to an embodiment, at least a two of the second dies are communicatively coupled to each other by a die to die interconnect formed entirely within a single sub region in the first die.Type: GrantFiled: April 1, 2017Date of Patent: October 18, 2022Assignee: Intel CorporationInventors: MD Altaf Hossain, Dinesh Somasekhar, Dheeraj Subbareddy
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Publication number: 20220326676Abstract: A circuit system includes a processing circuit, an accelerator circuit, and a buffer circuit that stores packets of data and that is coupled to the processing circuit and to the accelerator circuit. The buffer circuit functions as a crossbar circuit by allowing each of the accelerator circuit and the processing circuit to access at least one of the packets of data stored in the buffer circuit during access to another one of the packets of data stored in the buffer circuit.Type: ApplicationFiled: June 29, 2022Publication date: October 13, 2022Applicant: Intel CorporationInventors: Sreedhar Ravipalli, Mahesh Kumashikar, Md Altaf Hossain, Ankireddy Nalamalpu
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Publication number: 20220198115Abstract: Systems or methods of the present disclosure may improve scalability (e.g., component scalability, product variation scalability) of integrated circuit systems by disaggregating periphery intellectual property (IP) circuitry into modular periphery IP tiles that can be installed as modules. Such an integrated circuit system may include a first die that includes programmable fabric circuitry and a second die that that includes a periphery IP tile. The periphery IP tile may be disaggregated from the programmable fabric die and may be communicatively coupled to the first die via a modular interface.Type: ApplicationFiled: August 2, 2021Publication date: June 23, 2022Inventors: Chee Hak Teh, Ankireddy Nalamalpu, MD Altaf Hossain, Dheeraj Subbareddy, Sean R. Atsatt, Lai Guan Tang
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Patent number: 11342238Abstract: A multi-chip packaged device may include a first integrated circuit die with a first integrated circuit, such that the first integrated circuit may include a first plurality of ports disposed on a first side and a second plurality of ports disposed on a second side of the first integrated circuit die. The multi-chip packaged device may also include a second integrated circuit die, such that the second integrated circuit may include a third plurality of ports disposed on a third side of the second integrated circuit die. The first integrated circuit may communicate with the first side of the second integrated circuit when placed adjacent to the first side and communicate with the second side of the first integrated circuit die when placed adjacent to the second side.Type: GrantFiled: June 29, 2018Date of Patent: May 24, 2022Assignee: Intel CorporationInventors: MD Altaf Hossain, Ankireddy Nalamalpu, Dheeraj Subbareddy