Patents by Inventor Md M. Hoque
Md M. Hoque has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180260014Abstract: A memory system has a memory array divided into a plurality of sub-arrays in which each sub-array has a mutually exclusive power domain, task scheduler circuitry coupled to the memory array, and sub-array power control circuitry coupled to the task scheduler circuitry. A method includes selecting, by the task scheduler circuitry, a task for execution, providing a control signal to the sub-array power control circuitry indicative of a set of sub-arrays to power based on the selected task, and setting a power state of each sub-array, by the sub-array control circuitry, in response to the control signal.Type: ApplicationFiled: March 7, 2017Publication date: September 13, 2018Inventors: Patrice M. PARRIS, Weize CHEN, Md M. HOQUE, Frank Kelsey BAKER, JR., Victor WANG, Joachim Josef Maria KRUECKEN
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Patent number: 9991356Abstract: Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.Type: GrantFiled: August 24, 2016Date of Patent: June 5, 2018Assignee: NXP USA, Inc.Inventors: Weize Chen, Richard J. de Souza, Md M. Hoque, Patrice M. Parris
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Patent number: 9978689Abstract: An embodiment of an Ion Sensitive Field Effect Transistor (ISFET) structure includes a substrate, source and drain regions formed within the substrate and spatially separated by a channel region, a gate dielectric and a gate formed over the channel region, multiple conductive structures overlying the surface of the substrate, and one or more protection diode circuits coupled between one or more of the multiple conductive structures and the substrate. The multiple conductive structures include a floating gate structure and a sense plate structure. The floating gate structure is formed over the gate dielectric and includes the gate. The sense plate structure is electrically coupled to the floating gate structure and is configured to sense a concentration of a target ion or molecule in a fluid adjacent to a portion of the sense plate structure.Type: GrantFiled: December 18, 2013Date of Patent: May 22, 2018Assignee: NXP USA, INC.Inventors: Md M. Hoque, Patrice Parris, Weize Chen, Richard De Souza
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Patent number: 9964516Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.Type: GrantFiled: February 8, 2017Date of Patent: May 8, 2018Assignee: NXP USA, INC.Inventors: Patrice M. Parris, Weize Chen, Richard J. De Souza, Md M. Hoque, John M. McKenna
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Publication number: 20180059052Abstract: An ion sensor for sensing ions in a fluid includes a Metal-Oxide Semiconductor (MOS) varactor formed in and on a semiconductor substrate having a gate dielectric over the semiconductor substrate, a gate over the gate dielectric, a well region in the substrate under the gate dielectric, and source/drain regions in the well region, wherein the well region and the source/drain regions are of a same conductivity type; and a sense electrode coupled to the MOS varactor, wherein the capacitance of the gate dielectric of the varactor changes when the sense electrode interacts with ions in the fluid. Alternatively, resistance of the well region changes when the sense electrode interacts with ions in the fluid, affecting a change in a quality factor of an inductor.Type: ApplicationFiled: August 31, 2016Publication date: March 1, 2018Inventors: Md M. HOQUE, Weize CHEN, Patrice M. PARRIS
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Patent number: 9857329Abstract: Protected sensor field effect transistors (SFETs). The SFETs include a semiconductor substrate, a field effect transistor, and a sense electrode. The SFETs further include an analyte-receiving region that is supported by the semiconductor substrate, is in contact with the sense electrode, and is configured to receive an analyte fluid. The analyte-receiving region is at least partially enclosed. In some embodiments, the analyte-receiving region can be an enclosed analyte channel that extends between an analyte inlet and an analyte outlet. In these embodiments, the enclosed analyte channel extends such that the analyte inlet and the analyte outlet are spaced apart from the sense electrode. In some embodiments, the SFETs include a cover structure that at least partially encloses the analyte-receiving region and is formed from a cover material that is soluble within the analyte fluid. The methods include methods of manufacturing the SFETs.Type: GrantFiled: August 30, 2016Date of Patent: January 2, 2018Assignee: NXP USA, Inc.Inventors: Patrice M. Parris, Weize Chen, Richard J. de Souza, Jose Fernandez Villasenor, Md M. Hoque, David E. Niewolny, Raymond M. Roop
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Publication number: 20170146485Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.Type: ApplicationFiled: February 8, 2017Publication date: May 25, 2017Inventors: Patrice M. Parris, Weize Chen, Richard J. De Souza, Md M. Hoque, John M. McKenna
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Patent number: 9599587Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.Type: GrantFiled: September 5, 2014Date of Patent: March 21, 2017Assignee: NXP USA, INC.Inventors: Patrice M. Parris, Weize Chen, Richard J. De Souza, Md M. Hoque, John M. McKenna
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Patent number: 9541521Abstract: A mechanism is provided for enhancing the sensitivity of an ion-sensitive semiconductor device by creating a second gate coupled to a sense plate that can improve the amount of charge brought to the ion-sensitive semiconductor device conductivity modulated region (e.g., a channel region of an ISFET). This is accomplished by utilizing a buried dielectric layer associated with the ion-sensitive semiconductor device conductivity modulated region as the second gate dielectric. The buried dielectric layer is coupled to the sense plate using an isolated well region as a conductor that is coupled to metal layers extending to the sense plate. Some embodiments further use the buried dielectric layer as the sole gate dielectric for the semiconductor device, thereby allowing the traditional gate dielectric region to be coupled to a protection diode. This protection diode then protects the gate dielectric from plasma induced damage and electrostatic discharge.Type: GrantFiled: October 30, 2015Date of Patent: January 10, 2017Assignee: NXP USA, Inc.Inventors: Md M. Hoque, Weize Chen, Patrice M. Parris
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Publication number: 20160370314Abstract: Protected sensor field effect transistors (SFETs). The SFETs include a semiconductor substrate, a field effect transistor, and a sense electrode. The SFETs further include an analyte-receiving region that is supported by the semiconductor substrate, is in contact with the sense electrode, and is configured to receive an analyte fluid. The analyte-receiving region is at least partially enclosed. In some embodiments, the analyte-receiving region can be an enclosed analyte channel that extends between an analyte inlet and an analyte outlet. In these embodiments, the enclosed analyte channel extends such that the analyte inlet and the analyte outlet are spaced apart from the sense electrode. In some embodiments, the SFETs include a cover structure that at least partially encloses the analyte-receiving region and is formed from a cover material that is soluble within the analyte fluid. The methods include methods of manufacturing the SFETs.Type: ApplicationFiled: August 30, 2016Publication date: December 22, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Patrice M. Parris, Weize Chen, Richard J. de Souza, Jose Fernandez Villasenor, Md M. Hoque, David E. Niewolny, Raymond M. Roop
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Publication number: 20160365422Abstract: Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.Type: ApplicationFiled: August 24, 2016Publication date: December 15, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Weize Chen, Richard J. de Souza, Md M. Hoque, Patrice M. Parris
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Publication number: 20160356740Abstract: Protected sensor field effect transistors (SFETs). The SFETs include a semiconductor substrate, a field effect transistor, and a sense electrode. The SFETs further include an analyte-receiving region that is supported by the semiconductor substrate, is in contact with the sense electrode, and is configured to receive an analyte fluid. The analyte-receiving region is at least partially enclosed. In some embodiments, the analyte-receiving region can be an enclosed analyte channel that extends between an analyte inlet and an analyte outlet. In these embodiments, the enclosed analyte channel extends such that the analyte inlet and the analyte outlet are spaced apart from the sense electrode. In some embodiments, the SFETs include a cover structure that at least partially encloses the analyte-receiving region and is formed from a cover material that is soluble within the analyte fluid. The methods include methods of manufacturing the SFETs.Type: ApplicationFiled: June 5, 2015Publication date: December 8, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Patrice M. Parris, Weize Chen, Richard J. de Souza, Jose Fernandez Villasenor, Md M. Hoque, David E. Niewolny, Raymond M. Roop
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Patent number: 9494550Abstract: Protected sensor field effect transistors (SFETs). The SFETs include a semiconductor substrate, a field effect transistor, and a sense electrode. The SFETs further include an analyte-receiving region that is supported by the semiconductor substrate, is in contact with the sense electrode, and is configured to receive an analyte fluid. The analyte-receiving region is at least partially enclosed. In some embodiments, the analyte-receiving region can be an enclosed analyte channel that extends between an analyte inlet and an analyte outlet. In these embodiments, the enclosed analyte channel extends such that the analyte inlet and the analyte outlet are spaced apart from the sense electrode. In some embodiments, the SFETs include a cover structure that at least partially encloses the analyte-receiving region and is formed from a cover material that is soluble within the analyte fluid. The methods include methods of manufacturing the SFETs.Type: GrantFiled: June 5, 2015Date of Patent: November 15, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Patrice M. Parris, Weize Chen, Richard J. de Souza, Jose Fernandez Villasenor, Md M. Hoque, David E. Niewolny, Raymond M. Roop
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Patent number: 9437701Abstract: Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.Type: GrantFiled: October 27, 2014Date of Patent: September 6, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Weize Chen, Richard J. de Souza, Md M. Hoque, Patrice M. Parris
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Patent number: 9423376Abstract: A differential pair sensing circuit (300) includes control gates (306, 316) for separately programming a reference transistor (350) and a chemically-sensitive transistor (351) to a desired threshold voltage Vt to eliminate the mismatch between the transistors in order to increase the sensitivity and/or accuracy of the sensing circuit without increasing the circuit size.Type: GrantFiled: April 30, 2014Date of Patent: August 23, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Md M. Hoque, Patrice M. Parris, Weize Chen, Richard J. De Souza
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Publication number: 20160118469Abstract: Integrated circuit devices with counter-doped conductive gates. The devices have a semiconductor substrate that has a substrate surface. The devices also have a first well of a first conductivity type, a source of a second conductivity type, and a drain of the second conductivity type. A channel extends between the source and the drain. A conductive gate extends across the channel. The conductive gate includes a first gate region and a second gate region of the second conductivity type and a third gate region of the first conductivity type. The third gate region extends between the first and second gate regions. The devices further include a gate dielectric that extends between the conductive gate and the substrate and also include a silicide region in electrical communication with the first, second, and third gate regions. The methods include methods of manufacturing the devices.Type: ApplicationFiled: October 27, 2014Publication date: April 28, 2016Applicant: Freescale Semiconductor, Inc.Inventors: Weize Chen, Richard J. de Souza, Md M. Hoque, Patrice M. Parris
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Publication number: 20150316503Abstract: A differential pair sensing circuit (300) includes control gates (306, 316) for separately programming a reference transistor (350) and a chemically-sensitive transistor (351) to a desired threshold voltage Vt to eliminate the mismatch between the transistors in order to increase the sensitivity and/or accuracy of the sensing circuit without increasing the circuit size.Type: ApplicationFiled: April 30, 2014Publication date: November 5, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: Md M. Hoque, Patrice M. Parris, Weize Chen, Richard J. De Souza
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Publication number: 20150171018Abstract: An embodiment of an Ion Sensitive Field Effect Transistor (ISFET) structure includes a substrate, source and drain regions formed within the substrate and spatially separated by a channel region, a gate dielectric and a gate formed over the channel region, multiple conductive structures overlying the surface of the substrate, and one or more protection diode circuits coupled between one or more of the multiple conductive structures and the substrate. The multiple conductive structures include a floating gate structure and a sense plate structure. The floating gate structure is formed over the gate dielectric and includes the gate. The sense plate structure is electrically coupled to the floating gate structure and is configured to sense a concentration of a target ion or molecule in a fluid adjacent to a portion of the sense plate structure.Type: ApplicationFiled: December 18, 2013Publication date: June 18, 2015Inventors: MD M. HOQUE, PATRICE PARRIS, WEIZE CHEN, RICHARD DE SOUZA
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Publication number: 20140375370Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.Type: ApplicationFiled: September 5, 2014Publication date: December 25, 2014Inventors: PATRICE M. PARRIS, WEIZE CHEN, RICHARD J. DE SOUZA, MD M. HOQUE, JOHN M. MCKENNA
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Patent number: 8878257Abstract: An ISFET includes a control gate coupled to a floating gate in a CMOS device. The control gate, for example, a poly-to-well capacitor, is configured to receive a bias voltage and effect movement of a trapped charge between the control gate and the floating gate. The threshold voltage of the ISFET can therefore by trimmed to a predetermined value, thereby storing the trim information (the amount of trapped charge in the floating gate) within the ISFET itself.Type: GrantFiled: June 4, 2010Date of Patent: November 4, 2014Assignee: Freescale Semiconductor, Inc.Inventors: Patrice M. Parris, Weize Chen, Richard J. De Souza, Md M. Hoque, John M. McKenna