Patents by Inventor Meenakshi Gupta
Meenakshi Gupta has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230107541Abstract: Embodiments of the invention are directed to a system, method, or computer program product for dynamic authentication and processing of electronic activities based on parallel neural network processing. The invention provides a novel method for processing, in parallel, the activity data via a neuron cluster component, constructing an authentication level parameter associated with the parameter outputs for the first activity, and process the first activity based on at least determining that the authentication level parameter associated with the first activity is above a predetermined authentication threshold. In this regard, the invention is structured for neuron cluster bandwidth availability based input mapping and process channeling for dynamic detection of security events associated with network devices and resources and triggering real-time mitigation operations.Type: ApplicationFiled: October 5, 2021Publication date: April 6, 2023Applicant: BANK OF AMERICA CORPORATIONInventors: Prashant Anna Bidkar, Meenakshi Gupta, Prashant Khare, Kanika Manocha, Ankit Upadhyaya
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Publication number: 20230093450Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.Type: ApplicationFiled: November 30, 2022Publication date: March 23, 2023Inventors: Tzu-shun YANG, Rui CHENG, Karthik JANAKIRAMAN, Zubin HUANG, Diwakar KEDLAYA, Meenakshi GUPTA, Srinivas GUGGILLA, Yung-chen LIN, Hidetaka OSHIO, Chao LI, Gene LEE
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Patent number: 11527408Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.Type: GrantFiled: May 5, 2020Date of Patent: December 13, 2022Assignee: Applied Materials, Inc.Inventors: Tzu-shun Yang, Rui Cheng, Karthik Janakiraman, Zubin Huang, Diwakar Kedlaya, Meenakshi Gupta, Srinivas Guggilla, Yung-chen Lin, Hidetaka Oshio, Chao Li, Gene Lee
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Patent number: 11456173Abstract: Embodiments for processing a substrate are provided and include a method of trimming photoresist to provide photoresist profiles with smooth sidewall surfaces and to tune critical dimensions (CD) for the patterned features and/or a subsequently deposited dielectric layer. The method can include depositing a sacrificial structure layer on the substrate, depositing a photoresist on the sacrificial structure layer, and patterning the photoresist to produce a crude photoresist profile on the sacrificial structure layer. The method also includes trimming the photoresist with a plasma to produce a refined photoresist profile covering a first portion of the sacrificial structure layer while a second portion of the sacrificial structure layer is exposed, etching the second portion of the sacrificial structure layer to form patterned features disposed on the substrate, and depositing a dielectric layer on the patterned features.Type: GrantFiled: February 21, 2020Date of Patent: September 27, 2022Assignee: APPLIED MATERIALS, INC.Inventors: Meenakshi Gupta, Rui Cheng, Srinivas Guggilla, Karthik Janakiraman, Diwakar N. Kedlaya, Zubin Huang
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Patent number: 11315787Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a mandrel layer on a substrate, conformally forming a spacer layer on the mandrel layer, wherein the spacer layer is a doped silicon material, and patterning the spacer layer. In another embodiment, a method for forming features on a substrate includes conformally forming a spacer layer on a mandrel layer on a substrate, wherein the spacer layer is a doped silicon material, selectively removing a portion of the spacer layer using a first gas mixture, and selectively removing the mandrel layer using a second gas mixture different from the first gas mixture.Type: GrantFiled: March 17, 2020Date of Patent: April 26, 2022Assignee: Applied Materials, Inc.Inventors: Tzu-shun Yang, Rui Cheng, Karthik Janakiraman, Zubin Huang, Diwakar Kedlaya, Meenakshi Gupta, Srinivas Guggilla, Yung-chen Lin, Hidetaka Oshio, Chao Li, Gene Lee
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Publication number: 20200335339Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.Type: ApplicationFiled: May 5, 2020Publication date: October 22, 2020Inventors: Tzu-shun YANG, Rui CHENG, Karthik JANAKIRAMAN, Zubin HUANG, Diwakar KEDLAYA, Meenakshi GUPTA, Srinivas GUGGILLA, Yung-chen LIN, Hidetaka OSHIO, Chao LI, Gene LEE
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Publication number: 20200335338Abstract: The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a mandrel layer on a substrate, conformally forming a spacer layer on the mandrel layer, wherein the spacer layer is a doped silicon material, and patterning the spacer layer. In another embodiment, a method for forming features on a substrate includes conformally forming a spacer layer on a mandrel layer on a substrate, wherein the spacer layer is a doped silicon material, selectively removing a portion of the spacer layer using a first gas mixture, and selectively removing the mandrel layer using a second gas mixture different from the first gas mixture.Type: ApplicationFiled: March 17, 2020Publication date: October 22, 2020Inventors: Tzu-Shun YANG, Rui CHENG, Karthik JANAKIRAMAN, Zubin HUANG, Diwakar KADLAYA, Meenakshi GUPTA, Srinivas GUGGILLA, Yung-chen LIN, Hidetaka OSHIO, Chao LI, Gene LEE
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Publication number: 20200321210Abstract: Embodiments for processing a substrate are provided and include a method of trimming photoresist to provide photoresist profiles with smooth sidewall surfaces and to tune critical dimensions (CD) for the patterned features and/or a subsequently deposited dielectric layer. The method can include depositing a sacrificial structure layer on the substrate, depositing a photoresist on the sacrificial structure layer, and patterning the photoresist to produce a crude photoresist profile on the sacrificial structure layer. The method also includes trimming the photoresist with a plasma to produce a refined photoresist profile covering a first portion of the sacrificial structure layer while a second portion of the sacrificial structure layer is exposed, etching the second portion of the sacrificial structure layer to form patterned features disposed on the substrate, and depositing a dielectric layer on the patterned features.Type: ApplicationFiled: February 21, 2020Publication date: October 8, 2020Inventors: Meenakshi GUPTA, Rui CHENG, Srinivas GUGGILLA, Karthik JANAKIRAMAN, Diwakar N. KEDLAYA, Zubin HUANG
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Patent number: 10788856Abstract: Particular embodiments described herein provide for an electronic system that includes a docking station configured to wirelessly couple to an electronic device and a wireless charging element removably coupled to the docking station. The wireless charging element includes a power receiving unit and is configured to wireless charge the electronic device. In an example, the docking station is configured for high speed input/output.Type: GrantFiled: November 24, 2015Date of Patent: September 29, 2020Assignee: Intel CorporationInventors: Brian R. Peil, Russell S. Aoki, Aleksander Magi, James W. Edwards, Don J. Nguyen, Nicholas W. Oakley, Daria A. Loi, Meenakshi Gupta, Nithyananda S. Jeganathan
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Patent number: 10412560Abstract: Disclosed is a mobile device. The mobile device may be located proximate a mobile terminal and controlled by the mobile terminal. The mobile device may include a processor and a memory. The memory may store instructions that, when executed by the processor, cause the processor to: determine a mode of operation of the mobile device, determine a thermal profile for the mode of operation of the mobile device, and implement a power profile to achieve the thermal profile.Type: GrantFiled: September 29, 2016Date of Patent: September 10, 2019Assignee: Intel CorporationInventors: Ralph V. Miele, Eduardo Escamilla, James Utz, James M. Yoder, Tongyan Zhai, Baomin Liu, Meenakshi Gupta, Brian R Peil, Venkat R Gaurav, Drew G Damm, Andrew Larson, Ricky O Branner
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Publication number: 20180329572Abstract: The present disclosure is directed to autonomous determination of global touch event coordinates on a system that includes at least two touchscreen devices configured to display a scene in a collage display mode. In the collage display mode the image in a first touchscreen device is apportioned between and displayed on a plurality of touchscreen devices. The collage display mode beneficially provides enhanced resolution, greater fluidity, and less disruption or discontinuities as objects and/or moving objects included in the scene transition between touchscreen devices while enabling full touchscreen functionality across the plurality of touchscreen devices including the image displayed in collage mode.Type: ApplicationFiled: May 11, 2017Publication date: November 15, 2018Applicant: Intel CorporationInventors: Meenakshi Gupta, James Edwards
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Publication number: 20180307275Abstract: Particular embodiments described herein provide for an electronic system that includes a docking station configured to wirelessly couple to an electronic device and a wireless charging element removably coupled to the docking station. The wireless charging element includes a power receiving unit and is configured to wireless charge the electronic device. In an example, the docking station is configured for high speed input/output.Type: ApplicationFiled: November 24, 2015Publication date: October 25, 2018Applicant: Intel CorporationInventors: Brian R. Peil, Russell S. Aoki, Aleksander Magi, James W. Edwards, Don J. Nguyen, Nicholas W. Oakley, Daria A. Loi, Meenakshi Gupta, Nithyananda S. Jeganathan
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Publication number: 20180091987Abstract: Disclosed is a mobile device. The mobile device may be located proximate a mobile terminal and controlled by the mobile terminal. The mobile device may include a processor and a memory. The memory may store instructions that, when executed by the processor, cause the processor to: determine a mode of operation of the mobile device, determine a thermal profile for the mode of operation of the mobile device, and implement a power profile to achieve the thermal profile.Type: ApplicationFiled: September 29, 2016Publication date: March 29, 2018Inventors: Ralph V. Miele, Eduardo Escamilla, James Utz, James M. Yoder, Tongyan Zhai, Baomin Liu, Meenakshi Gupta, Brian R. Peil, Venkat R. Gaurav, Drew G. Damm, Andrew Larson, Ricky O. Branner, Steven J. Lofland, George H. Daskalakis, James C. Raupp, Michael Ahrens, David Pidwerbecki, Bo Qiu, Stacy L. Yee
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Patent number: 9690340Abstract: A system and method for adaptive thermal and performance management in electronic devices are disclosed. A particular embodiment includes: providing a processor with a plurality of selectable performance levels and a sensor in an electronic device; receiving sensor information from the sensor, the sensor information including information for determining if the electronic device is positioned proximately to an active airflow; determining a device context from the sensor information; and dynamically modifying the performance level of the processor by implementing one of a plurality of selectable performance levels of the processor based on the device context.Type: GrantFiled: March 26, 2015Date of Patent: June 27, 2017Assignee: Intel CorporationInventors: James W. Edwards, Meenakshi Gupta, Brian R. Peil, Nicholas R. Weber, Nicolas A. Kurczewski
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Patent number: 9357576Abstract: Systems and methods may provide for establishing automatic pairing between a portable computing device and a base device. A processor is configured to receive a dock event notification when the portable computing device docks with the base device. An identifier retriever is configured to retrieve the identifier of a wireless communication component in a base device. A pairing portion of the processor is configured to automatically pair a wireless communication component in a portable computing device with the wireless communication component in the base device. Automatic wireless connection may follow automatic pairing.Type: GrantFiled: September 27, 2014Date of Patent: May 31, 2016Assignee: Intel CorporationInventors: Meenakshi Gupta, James W. Edwards, Bryan Y. Roe
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Publication number: 20160091938Abstract: A system and method for adaptive thermal and performance management in electronic devices are disclosed. A particular embodiment includes: providing a processor with a plurality of selectable performance levels and a sensor in an electronic device; receiving sensor information from the sensor, the sensor information including information for determining if the electronic device is positioned proximately to an active airflow; determining a device context from the sensor information; and dynamically modifying the performance level of the processor by implementing one of a plurality of selectable performance levels of the processor based on the device context.Type: ApplicationFiled: March 26, 2015Publication date: March 31, 2016Applicant: INTEL CORPORATIONInventors: James W. Edwards, Meenakshi Gupta, Brian R. Peil, Nicholas R. Weber, Nicolas A. Kurczewski
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Publication number: 20160095145Abstract: Systems and methods may provide for establishing automatic pairing between a portable computing device and a base device. A processor is configured to receive a dock event notification when the portable computing device docks with the base device. An identifier retriever is configured to retrieve the identifier of a wireless communication component in a base device. A pairing portion of the processor is configured to automatically pair a wireless communication component in a portable computing device with the wireless communication component in the base device. Automatic wireless connection may follow automatic pairing.Type: ApplicationFiled: September 27, 2014Publication date: March 31, 2016Inventors: Meenakshi Gupta, James W. Edwards, Bryan Y. Roe