Abstract: A method and system is provided to enable quality of service across a backplane switch for multicast packets. For multicast traffic, an egress queue manager manages congestion control in accordance with multicast scheduling flags. A multicast scheduling flag is associated with each egress queue capable of receiving a packet from a multicast ingress queue. When the multicast scheduling flag is set and the congested egress queue is an outer queue, the egress queue manager refrains from dequeueing any marked multicast packets to the destination ports associated with the congested outer queue until the congestion subsides. When the congested egress queue is a backplane queue, the egress queue manager refrains from dequeuing any marked multicast packets to the destination ports on the destination blade associated with the congested backplane queue until the congestion subsides.

Abstract: Methods and systems for fine grain bandwidth allocation are disclosed. According to one method, input is received from a user in a standard bandwidth denomination indicating bandwidth to be provided by a switched network element. The bandwidth is automatically converted into a base bandwidth value and a residual bandwidth value. The base bandwidth value is converted to a number of tokens to be placed in a token bucket every predetermined token bucket refresh interval. The residual bandwidth value is converted into a second number of tokens and a number of predetermined token bucket refresh intervals over which the second number of tokens is to be placed in the token buckets. The token buckets are then refreshed in accordance with the base and residual bandwidth values and the token bucket refresh intervals. The queue is serviced in accordance with available tokens in the token buckets.

Abstract: A method and system is provided to enable quality of service across a backplane switch. An egress queue manager on one blade communicates with an ingress queue manager on the same or on another blade where each blade is connected via a backplane switch. The egress queue managers communicate the congestion to ingress queue managers using a messaging scheme. The ingress queue managers determine when to reduce or resume the packet sending rates of ingress queues mapped to congested egress queues or to destinations on congested blades. Each ingress queue manager maintains information about the status of egress queue congestion on its own blades. Normal rates of dequeuing packets from ingress queues are resumed only when the related congestion on all of the egress queues or related destinations has subsided.

Abstract: A method and system is provided to enable quality of service across a backplane switch. An egress queue manager on one blade communicates with an egress queue manager on another blade where each blade is connected via a backplane switch. When a blade becomes congested, egress queues mapped to a destination on the congested blade also become congested. The egress queue managers determine when to reduce or resume the packet sending rates of egress queues mapped to destinations on congested blades using a messaging scheme. Each egress queue manager maintains notifications of the status of egress queue congestion on its own and other blades. Normal rates of dequeuing packets are resumed only when the related congestion on all of the blades has subsided.

Abstract: A method and system is provided to enable quality of service across a backplane switch for multicast packets. For multicast traffic, an egress queue manager manages congestion control in accordance with multicast scheduling flags. A multicast scheduling flag is associated with each egress queue capable of receiving a packet from a multicast ingress queue. When the multicast scheduling flag is set and the congested egress queue is an outer queue, the egress queue manager refrains from dequeueing any marked multicast packets to the destination ports associated with the congested outer queue until the congestion subsides. When the congested egress queue is a backplane queue, the egress queue manager refrains from dequeuing any marked multicast packets to the destination ports on the destination blade associated with the congested backplane queue until the congestion subsides.

Abstract: A multiple-way cache memory having a plurality of cache blocks and associated tag arrays includes a select circuit that stores way select values for each cache block. The way select values selectively disable one or more cache blocks from participating in cache operations by forcing tag comparisons associated with the disabled cache blocks to a mismatch condition so that the disabled cache blocks will not be selected to provide output data. The remaining enabled cache blocks may be operated as a less-associative cache memory without requiring cache addressing modifications.

Abstract: A multiple-way cache memory having a plurality of cache blocks and associated tag arrays includes a select circuit that stores way select values for each cache block. The way select values selectively disable one or more cache blocks from participating in cache operations by forcing tag comparisons associated with the disabled cache blocks to a mismatch condition so that the disabled cache blocks will not be selected to provide output data. The remaining enabled cache blocks may be operated as a less-associative cache memory without requiring cache addressing modifications.

Abstract: A multiprocessor system includes a plurality of central processing units (CPUs) connected to one another by a system bus. Each CPU includes a cache controller to communicate with its cache, and a primary memory controller to communicate with its primary memory. When there is a cache miss in a CPU, the cache controller routes an address request for primary memory directly to the primary memory via the CPU as a speculative request without access the system bus, and also issues the address request to the system bus to facilitate data coherency. The speculative request is queued in the primary memory controller, which in turn retrieves speculative data from a specified primary memory address. The CPU monitors the system bus for a subsequent transaction that requests the specified data in the primary memory. If the subsequent transaction requesting the specified data is a read transaction that corresponds to the speculative address request, the speculative request is validated and becomes non-speculative.

Abstract: The main cache of a processor in a multiprocessor computing system is coupled to receive writeback data during writeback operations. In one embodiment, during writeback operations, e.g., for a cache miss, dirty data in the main cache is merged with modified data from an associated write cache, and the resultant writeback data line is loaded into a writeback buffer. The writeback data is also written back into the main cache, and is maintained in the main cache until replaced by new data. Subsequent requests (i.e., snoops) for the data are then serviced from the main cache, rather than from the writeback buffer. In some embodiments, further modifications of the writeback data in the main cache are prevented. The writeback data line in the main cache remains valid until read data for the cache miss is returned, thereby ensuring that the read address reaches the system interface for proper bus ordering before the writeback line is lost.

Abstract: A cache memory system having a cache and a cache tag. A cache tag cache is provided to store a subset of the most recently or frequently used cache tags. The cache tag cache is accessed during tag inquires in a manner similar to conventional cache tag inquires. Hits in the cache tag cache have a lower access latency than the tag lookups that miss and require access to the cache tag.

Abstract: A cache memory system including a cache memory having a plurality of cache lines. An index portion of a tag array includes an n-bit pointer entry for every cache line. A shared tag portion of a tag array includes a number of entries, where each entry includes shared tag information that is shared among a plurality of the cache lines. Each n-bit pointer in the index portion of the tag array points into an entry in the shared tag portion.

Abstract: A cache system including a data cache memory comprising a plurality of cache lines. A tag store has an entry representing each line in the cache memory where each entry comprises tag information for accessing the data cache. The tag information includes state information indicating whether the represented cache line includes dirty data. A speculative write back unit monitors the state information and is operative to initiate a write back of a cache line having more than a preselected amount of dirty data.

Abstract: An automated method and system for detecting electromigration violations in signal lines of an integrated circuit design to be fabricated is disclosed. The automated method and system checks conductive traces, vias and/or contacts that are used to route signals to and from various functional cells within the integrated circuit design against predetermined process rules to detect electromigration violations. The operation and effectiveness of the automated method and system are far superior to conventional manual approaches.