Patents by Inventor Meera Viswanath

Meera Viswanath has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Low-power static signoff verification from within an implementation tool
    Patent number: 11947885
    Abstract: In one aspect, a method includes invoking a signoff tool via a first command from an implementation tool running on a register transfer level (RTL) design, and executing a native command of the signoff tool from within the implementation tool. The native command generates a notification. The method also includes determining whether the RTL design passes a low-power signoff check based on the notification and sending the design for final signoff verification based on the determination that the RTL design passes the low-power signoff checks.
    Type: Grant
    Filed: September 22, 2021
    Date of Patent: April 2, 2024
    Assignee: SYNOPSYS, INC.
    Inventors: Meera Viswanath, David Allen, Sabyasachi Das, Kaushik De, Renu Mehra, Godwin R. Maben