Patents by Inventor Meg Hung

Meg Hung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Intermediate layout for resolution enhancement in semiconductor fabrication
    Patent number: 7979811
    Abstract: Intermediate resolution-enhancement state layouts are generated based upon an original non-resolution enhanced layout of an integrated circuit and an associated resolution-enhanced layout. The intermediate resolution-enhancement state layout includes fragments corresponding to parts of the original layout and biases associated with the fragments, where the biases indicate distances between the fragments and the resolution-enhanced layout. The fragments are also assigned attributes such as fragment type, fragment location, and biases. The intermediate resolution-enhancement state layouts can be combined to generate the layout for a full chip IC. Two or more intermediate resolution-enhancement state layouts are assembled and are locally reconverged to adjust the resolution enhancement associated with the intermediate resolution-enhancement state layouts and obtain the intermediate resolution-enhancement state layouts for the full IC.
    Type: Grant
    Filed: April 8, 2008
    Date of Patent: July 12, 2011
    Assignee: Tela Innovations, Inc.
    Inventors: Shao-Po Wu, Xin Wang, Hongbo Tang, Meg Hung
  • Intermediate Layout for Resolution Enhancement in Semiconductor Fabrication
    Publication number: 20080216047
    Abstract: Intermediate resolution-enhancement state layouts are generated based upon an original non-resolution enhanced layout of an integrated circuit and an associated resolution-enhanced layout. The intermediate resolution-enhancement state layout includes fragments corresponding to parts of the original layout and biases associated with the fragments, where the biases indicate distances between the fragments and the resolution-enhanced layout. The fragments are also assigned attributes such as fragment type, fragment location, and biases. The intermediate resolution-enhancement state layouts can be combined to generate the layout for a full chip IC. Two or more intermediate resolution-enhancement state layouts are assembled and are locally reconverged to adjust the resolution enhancement associated with the intermediate resolution-enhancement state layouts and obtain the intermediate resolution-enhancement state layouts for the full IC.
    Type: Application
    Filed: April 8, 2008
    Publication date: September 4, 2008
    Applicant: APRIO TECHNOLOLGIES, INC.
    Inventors: Shao-Po Wu, Xin Wang, Hongbo Tang, Meg Hung
  • Intermediate layout for resolution enhancement in semiconductor fabrication
    Patent number: 7404173
    Abstract: Intermediate resolution-enhancement state layouts are generated based upon an original non-resolution enhanced layout of an integrated circuit and an associated resolution-enhanced layout. The intermediate resolution-enhancement state layout includes fragments corresponding to parts of the original layout and biases associated with the fragments, where the biases indicate distances between the fragments and the resolution-enhanced layout. The fragments are also assigned attributes such as fragment type, fragment location, and biases. The intermediate resolution-enhancement state layouts can be combined to generate the layout for a full chip IC. Two or more intermediate resolution-enhancement state layouts are assembled and are locally reconverged to adjust the resolution enhancement associated with the intermediate resolution-enhancement state layouts and obtain the intermediate resolution-enhancement state layouts for the full IC.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: July 22, 2008
    Assignee: Aprio Technologies, Inc.
    Inventors: Shao-Po Wu, Xin Wang, Hongbo Tang, Meg Hung
  • Intermediate layout for resolution enhancement in semiconductor fabrication
    Publication number: 20050229131
    Abstract: Intermediate resolution-enhancement state layouts are generated based upon an original non-resolution enhanced layout of an integrated circuit and an associated resolution-enhanced layout. The intermediate resolution-enhancement state layout includes fragments corresponding to parts of the original layout and biases associated with the fragments, where the biases indicate distances between the fragments and the resolution-enhanced layout. The fragments are also assigned attributes such as fragment type, fragment location, and biases. The intermediate resolution-enhancement state layouts can be combined to generate the layout for a full chip IC. Two or more intermediate resolution-enhancement state layouts are assembled and are locally reconverged to adjust the resolution enhancement associated with the intermediate resolution-enhancement state layouts and obtain the intermediate resolution-enhancement state layouts for the full IC.
    Type: Application
    Filed: March 7, 2005
    Publication date: October 13, 2005
    Inventors: Shao-Po Wu, Xin Wang, Hongbo Tang, Meg Hung
  • Method and apparatus for selective, incremental, reconfigurable and reusable semiconductor manufacturing resolution-enhancements
    Publication number: 20050229130
    Abstract: An automated design for manufacturability platform for integrated physical verification and manufacturing enhancement operations. Given original layouts and one or more associated resolution-enhanced layouts, intermediate resolution-enhancement state layouts are reconstructed, and selective localized resolution-enhancement reconfigurations, modifications, and/or perturbations are introduced on any existing enhancements in order to improve manufacturability and yield.
    Type: Application
    Filed: April 7, 2004
    Publication date: October 13, 2005
    Applicant: Aprio Technologies, Inc.
    Inventors: Shao-Po Wu, Xin Wang, Hongbo Tang, Meg Hung