Abstract: A wireless power transmitting system includes a power amplifier comprising a plurality of measurement points and a power amplifier controller integrated circuit (IC). In some embodiments, the power amplifier controller IC performs synchronization of the various components of the power amplifier, conducts impedance and temperature measurements at the measurements points, determines if a foreign object is within the transmission range of the wireless power transmitter, and decides if a shutdown of the power amplifier is needed. In some embodiments, the power amplifier controller IC determines through a transmitter controller IC, the presence of a foreign object within the transmission range and adjusts the power transmission to one or more receivers.

Abstract: A wireless power transmitting system includes a power amplifier comprising a plurality of measurement points and a power amplifier controller integrated circuit (IC). In some embodiments, the power amplifier controller IC performs synchronization of the various components of the power amplifier, conducts impedance and temperature measurements at the measurements points, determines if a foreign object is within the transmission range of the wireless power transmitter, and decides if a shutdown of the power amplifier is needed. In some embodiments, the power amplifier controller IC determines through a transmitter controller IC, the presence of a foreign object within the transmission range and adjusts the power transmission to one or more receivers.

Abstract: A wireless power transmitting system includes a power amplifier comprising a plurality of measurement points and a power amplifier controller integrated circuit (IC). In some embodiments, the power amplifier controller IC performs synchronization of the various components of the power amplifier, conducts impedance and temperature measurements at the measurements points, determines if a foreign object is within the transmission range of the wireless power transmitter, and decides if a shutdown of the power amplifier is needed. In some embodiments, the power amplifier controller IC determines through a transmitter controller IC, the presence of a foreign object within the transmission range and adjusts the power transmission to one or more receivers.

Abstract: A wireless power transmitting system includes a power amplifier comprising a plurality of measurement points and a power amplifier controller integrated circuit (IC). In some embodiments, the power amplifier controller IC performs synchronization of the various components of the power amplifier, conducts impedance and temperature measurements at the measurements points, determines if a foreign object is within the transmission range of the wireless power transmitter, and decides if a shutdown of the power amplifier is needed. In some embodiments, the power amplifier controller IC determines through a transmitter controller IC, the presence of a foreign object within the transmission range and adjusts the power transmission to one or more receivers.

Abstract: A wireless power transmitting system includes a power amplifier comprising a plurality of measurement points and a power amplifier controller integrated circuit (IC). In some embodiments, the power amplifier controller IC performs synchronization of the various components of the power amplifier, conducts impedance and temperature measurements at the measurements points, determines if a foreign object is within the transmission range of the wireless power transmitter, and decides if a shutdown of the power amplifier is needed. In some embodiments, the power amplifier controller IC determines through a transmitter controller IC, the presence of a foreign object within the transmission range and adjusts the power transmission to one or more receivers.

Abstract: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.

Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.

Abstract: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.

Abstract: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.

Abstract: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.

Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.

Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.

Abstract: Embodiments provide a reference-less frequency detector that overcomes the “dead zone” problem of conventional circuits. In particular, the frequency detector is able to accurately resolve the polarity of the frequency difference between the VCO clock signal and the data signal, irrespective of the magnitude of the frequency difference and the presence of VCO clock jitter and/or ISI on the data signal.

Abstract: Embodiments of a flash analog-to-digital converter (ADC) that can detect and suppress bubbles in a thermometer code of a flash ADC are provided herein. Bubbles can result in large sparkle errors, which degrade the bit error rates (BER) of flash ADCs. The present invention utilizes a bubble correction module that is configured to provide a bubble corrected one-of-N code by suppressing at least one of any two tops that are not separated by at least two levels within a one-of-N code.

Abstract: Embodiments of a flash analog-to-digital converter (ADC) that can detect and suppress bubbles in a thermometer code of a flash ADC are provided herein. Bubbles can result in large sparkle errors, which degrade the bit error rates (BER) of flash ADCs. The present invention utilizes a bubble correction module that is configured to provide a bubble corrected one-of-N code by suppressing at least one of any two tops that are not separated by at least two levels within a one-of-N code.